CMOS, 8-Bit, Buffered Multiplying DAC Enhanced Product AD7524-EP FEATURES FUNCTIONAL BLOCK DIAGRAM V DD Microprocessor compatible (6800, 8085, Z80) 14 TTL-/CMOS-compatible inputs 10k 10k 10k V 15 REF On-chip data latches 20k 20k 20k 20k 20k Endpoint linearity Low power consumption 10k S1 S2 S3 S8 16 R FB Monotonicity guaranteed (full temperature range) 1 OUT1 Latch free (no protection Schottky required) OUT2 2 ENHANCED PRODUCT FEATURES CHIP SELECT 12 DATA LATCHES 3 GND WRITE 13 Supports defense and aerospace applications (AQEC) AD7524-EP Military temperature range (55C to +125C) 4 5 6 3 Controlled manufacturing baseline DB7 DB6 DB5 DB0 (MSB) (LSB) One assembly/test site DATA INPUTS One fabrication site Figure 1. Product change notification Qualification data available on request APPLICATIONS Microprocessor controlled gain circuits Microprocessor controlled attenuator circuits Microprocessor controlled function generation Precision AGC circuits Bus structured instruments GENERAL DESCRIPTION The AD7524-EP is a low cost, 8-bit monolithic CMOS DAC Featuring operation from 5 V to 15 V, the AD7524-EP interfaces designed for direct interface to most microprocessors. directly to most microprocessor buses or output ports. An 8-bit DAC with input latches, the load cycle of the AD7524-EP Excellent multiplying characteristics (2- or 4-quadrant) make is similar to the write cycle of the random access memory. Using the AD7524-EP an ideal choice for many microprocessor an advanced thin-film on the CMOS fabrication process, the controlled gain setting and signal control applications. AD7524-EP provides accuracy to LSB with a typical power Additional application and technical information can be found dissipation of less than 10 mW. in the AD7524 data sheet. An improved design eliminates the protection Schottky previously required and guarantees TTL compatibility when using a 5 V supply. The loading speed has also been increased for compatibility with most microprocessors. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 01132-001AD7524-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Write Cycle Timing Diagram.......................................................4 Enhanced Product Features ............................................................ 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................6 General Description ......................................................................... 1 Outline Dimensions ..........................................................................7 Revision History ............................................................................... 2 Ordering Guide .............................................................................7 Specifications ..................................................................................... 2 REVISION HISTORY 3/2018 Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Changes to Ordering Guide ............................................................ 7 1/2012Revision 0: Initial Version Rev. A Page 2 of 7