16-Bit a DSP DACPORT AD766 FEATURES Zero-Chip Interface to Digital Signal Processors FUNCTIONAL BLOCK DIAGRAM Complete DACPORT On-Chip Voltage Reference Voltage and Current Outputs Serial, Twos-Complement Input 63 V Output Sample Rates to 390 kSPS 94 dB Minimum Signal-to-Noise Ratio 81 dB Maximum Total Harmonic Distortion 15-Bit Monotonicity 65 V to 612 V Operation 16-Pin Plastic and Ceramic Packages Available in Commercial, Industrial, and Military Temperature Ranges APPLICATIONS Digital Signal Processing Noise Cancellation Radar Jamming Automatic Test Equipment Precision Industrial Equipment The serial interface consists of bit clock, data, and latch enable Waveform Generation inputs. The twos-complement data word is clocked MSB first on falling clock edges into the serial-to-parallel converter, con- sistent with the serial protocols of popular DSP processors. The PRODUCT DESCRIPTION input clock can support data transfers up to 12.5 MHz. The The AD766 16-bit DSP DACPORT provides a direct, three- falling edge of latch enable updates the internal DAC input reg- wire interface to the serial ports of popular DSP processors, in- ister at the sample rate with the sixteen bits most recently cluding the ADSP-2101, TMS320CXX, and DSP56001. No clocked into the serial input register. additional glue logic is required. The AD766 is also com- The AD766 operates over a 5 V to 12 V power supply range. plete, offering on-chip serial-to-parallel input format conver- The digital supplies, +V and V , can be separated from the L L sion, a 16-bit current-steering DAC, voltage reference, and a analog signal supplies, +V and V , for reduced digital S S voltage output op amp. The AD766 is fabricated in Analog crosstalk. Separate analog and digital ground pins are also pro- Devices BiMOS II mixed-signal process which provides bipolar vided. An internal bandgap reference provides a precision volt- transistors, MOS transistors, and thin-film resistors for preci- age source to the output amp that is stable over temperature and sion analog circuits in addition to CMOS devices for logic. time. The design and layout of the AD766 have been optimized for ac Power dissipation is typically 120 mW with 5 V supplies and performance and are responsible for its guaranteed and tested 300 mW with 12 V. The AD766 is available in commercial 94 dB signal-to-noise ratio to 20 kHz and 79 dB SNR to (0C to +70C), industrial (40C to +85C), and military 250 kHz. Laser-trimming the AD766s silicon chromium thin- (55C to +125C) grades. Commercial and industrial grade film resistors reduces total harmonic distortion below 81 dB parts are available in a 16-pin plastic DIP military parts pro- (at 1 kHz), a specification also production tested. An optional cessed to MIL-STD-883B are packaged in a 16-pin ceramic linearity trim pin allows elimination of midscale differential DIP. See Analog Devices Military Products Databook or current linearity error for even lower THD with small signals. military data sheet for specifications for the military version. The AD766s output amplifier provides a 3 V signal with a high slew rate, small glitch, and fast settling. The output ampli- fier is short circuit protected and can withstand indefinite shorts to ground. DACPORT is a registered trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(T to T , 65 V supplies, F = 500 kSPS unless otherwise noted. No deglitchers or MIN MAX S AD766SPECIFICATIONS MSB trimming is used.) AD766J AD766A Parameter Min Typ Max Min Typ Max Units RESOLUTION 16 16 Bits DIGITAL INPUTS V 2.0 +V 2.0 +V V IH L L V 0.8 0.8 V IL I , V = V 1.0 1.0 A IH IH L I , V = 0.4 10 10 A IL IL SERIAL PORT TIMING Serial Clock Period (t ) 95 115 ns CLK Serial Clock HI (t)30 30 ns HI Serial Clock LO (t)30 70 ns LO Data Valid (t)40 40 ns DATA Data Setup (t)15 20 ns S Data Hold (t)15 20 ns H Clock-to-Latch-Enable (t ) 80 100 ns CTLE Latch-Enable-to-Clock (t)15 15 ns LETC Latch Enable HI (t)40 40 ns LEHI Latch Enable LO (t)40 80 ns LELO 1 ACCURACY Gain Error 2.0 2.0 % of FSR Gain Drift 25 25 ppm of FSR/C Midscale Output Voltage Error 30 30 mV Bipolar Zero Drift 4 4 ppm of FSR/C Differential Linearity Error 0.001 0.001 % of FSR Monotonicity 15 15 Bits TOTAL HARMONIC DISTORTION 1 F = 1037 Hz OU T 0 dB 88 81 88 81 dB 20 dB 75 65 75 65 dB 60 dB 37 27 37 27 dB 2 F = 49.07 kHz OUT 0 dB 77 72 77 72 dB 20 dB 69 66 69 66 dB 60 dB 25 21 25 21 dB 3 SIGNAL-TO-NOISE RATIO 1 20 Hz to 20 kHz (F = 1037 Hz) 94 102 94 102 dB OUT 2 20 kHz to 250 kHz (F = 49.07 kHz) 79 83 79 83 dB OUT SETTLING TIME (to 0.0015% of FSR) 1 Voltage Output 6 V Step 1.5 1.5 s 1 LSB Step 1.0 1.0 s Slew Rate 9 9 V/s Current Output 1 mA Step 10 to 100 Load 350 350 ns 1 k Load 350 350 ns OUTPUT 1 Voltage Output Configuration Bipolar Range 2.88 3.0 3.12 2.88 3.0 3.12 V Output Current 8.0 8.0 mA Output Impedance 0.1 0.1 Short Circuit Duration Indefinite to Common Indefinite to Common Current Output Configuration Bipolar Range 0.7 1.0 1.3 0.7 1.0 1.3 mA Output Impedance (30%) 1.7 1.7 k POWER SUPPLY Voltage: +V and +V 4.75 13.2 4.75 13.2 V L S Voltage: V and V 13.2 4.75 13.2 4.75 V L S 1 Current Case 1 : V and V = +5 V +I 12.0 15.0 12.0 15.0 mA S L 1 Current Case 1 : V and V = 5 V I 12.0 15.0 12.0 15.0 mA S L 1 Current Case 2: V and V = +12 V +I 10.5 10.5 mA S L 1 Current Case 2: V and V = 12 V I 14 14 mA S L 4 Current Case 3 : V and V = +5 V +I 12 12 mA S L 1 Current Case 2: V and V = 12 V I 14 14 mA S L 1 Power Dissipation: V and V = 5 V 120 150 120 150 mW S L Power Dissipation: V and V = 12 V 300 300 mW S L Power Dissipation: V and V = +5 V, S L 4 Power Dissipation: V and V = 12 V 225 225 mW S L 2 REV. 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