3 V/5 V Low Power, Synchronous a Voltage-to-Frequency Converter AD7740* FEATURES FUNCTIONAL BLOCK DIAGRAM Synchronous Operation Full-Scale Frequency Set by External System Clock REFIN/OUT VDD 8-Lead SOT-23 and 8-Lead M S O P Packages 3 V or 5 V Operation AD7740 2.5V Low Power: 3 mW (Typ) REFERENCE Nominal Input Range: 0 to V REF True 150 mV Capability Without Charge Pump V Range: 2.5 V to VDD REF VOLTAGE-TO- X1 VIN FREQUENCY Internal 2.5 V Reference FOUT MODULATOR 1 MHz Max Input Frequency Selectable High Impedance Buffered Input Minimal External Components Required CLOCK GENERATION APPLICATIONS Isolation of High Common-Mode Voltages Low-Cost Analog-to-Digital Conversion BUF CLKOUT CLKIN GND Battery Monitoring Automotive Sensing GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7740 is a low-cost, ultrasmall synchronous Voltage-to- 1. The AD7740 is a single channel, single-ended VFC. It is Frequency Converter (VFC). It works from a single 3.0 V to available in 8-lead SOT-23 and 8-lead MSOP packages, and is 3.6 V or 4.75 V to 5.25 V supply consuming 0.9 mA. The AD7740 intended for low-cost applications. The AD7740 offers is available in an 8-lead SOT-23 and also in an 8-lead MSOP considerable space saving over alternative solutions. package. Small package, low cost and ease of use were major 2. The AD7740 operates from a single 3.0 V to 3.6 V or 4.75 V design goals for this product. The part contains an on-chip 2.5 V to 5.25 V supply and consumes typically 0.9 mA when the bandgap reference but the user may overdrive this using an input is unbuffered. It also contains an automatic power-down external reference. This external reference range includes VDD. function. The full-scale output frequency is synchronous with the clock 3. The AD7740 does not require external resistors and capaci- signal on the CLKIN pin. This clock can be generated with the tors to set the output frequency. The maximum output addition of an external crystal (or resonator) or supplied from a frequency is set by a crystal or a clock. No trimming or cali- CMOS-compatible clock source. The part has a maximum bration is required. input frequency of 1 MHz. 4. The analog input can be taken to 150 mV below GND for For an analog input signal that goes from 0 V to V , the out- REF true bipolar operation. put frequency goes from 10% to 90% of f In buffered mode, CLKIN. the part provides a very high input impedance and accepts a 5. The specied voltage reference range on REFIN is from range of 0.1 V to VDD 0.2 V on the VIN pin. There is also 2.5 V to the supply voltage, VDD. an unbuffered mode of operation that allows VIN to go from 0.15 V to VDD + 0.15 V. The modes are interchangeable using the BUF pin. The AD7740 (Y Grade) is guaranteed over the automotive temperature range of 40C to +105C. The AD7740 (K Grade) is guaranteed from 0C to 85C. *Protected under U.S. Patent 6,147,528. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20012016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. (VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V CLKIN = 1 MHz All AD7740 SPECIFICATIONS specifications T to T unless otherwise noted.) MIN MAX 1 K, Y Versions 2 Parameter Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE Integral Nonlinearity 3 4 CLKIN = 32 kHz 0.012 % of Span Unbuffered Mode, External Clock at CLKIN CLKIN = 1 MHz 0.012 % of Span Unbuffered Mode, Crystal at CLKIN 3 CLKIN = 32 kHz 0.018 % of Span Buffered Mode, External Clock at CLKIN CLKIN = 1 MHz 0.018 % of Span Buffered Mode, Crystal at CLKIN Offset Error 7 35 mV Unbuffered Mode, VIN = 0 V 7 35 mV Buffered Mode, VIN = 0.1 V Gain Error 0.1 0.7 % of Span 3 Offset Error Drift 20 V/C 3 Gain Error Drift 4 ppm of Span/C 3 Power Supply Rejection Ratio 55 dB VDD = 5% (5 V) 65 dB VDD = 10% (3.3 V) ANALOG INPUT, VIN Nominal Input Span 0 V V 150 mV Overrange Available REF 0.1 VDD 0.2 V Buffered Mode Input Current 8 10 A Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V 5 100 nA Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V REFERENCE VOLTAGE 5 REFIN Nominal Input Voltage 2.5 VDD V REFOUT Output Voltage 2.3 2.5 2.7 V 3 Output Impedance 1k See Pin Function Description 3 Reference Drift 50 ppm/C 3 Line Rejection 75 dB VDD = 5% (5 V) 3 Line Rejection 60 dB VDD = 10% (3.3 V) 3 Reference Noise (0.1 Hz to 10 Hz) 100 V pp FOUT OUTPUT Nominal Frequency Span 0.1 f to 0.9 f Hz VIN = 0 V to V . See Figure 2 CLKIN CLKIN REF 3 LOGIC INPUTS (CLKIN, BUF) CLKIN Input Frequency 32 1000 kHz For Specied Performance Input High Voltage, V 3.5 V VDD = 5 V 5% IH Input High Voltage, V 2.5 V VDD = 3.3 V 10% IH Input Low Voltage, V 0.8 V VDD = 5 V 5% IL Input Low Voltage, V 0.4 V VDD = 3.3 V 10% IL Input Current 2 A VIN = 0 V to V DD Pin Capacitance 3 10 pF BUF Input High Voltage, V 2.4 V VDD = 5 V 5% IH Input High Voltage, V 2.1 V VDD = 3.3 V 10% IH Input Low Voltage, V 0.8 V VDD = 5 V 5% IL Input Low Voltage, V 0.4 V VDD = 3.3 V 10% IL Input Current 100 nA Pin Capacitance 3 10 pF 3 LOGIC OUTPUTS (FOUT, CLKOUT) 6 Output High Voltage, V 4.0 V Output Sourcing 200 A . VDD = 5 V 5% OH 6 Output High Voltage, V 2.1 V Output Sourcing 200 A . VDD = 3.3 V 10% OH 6 Output Low Voltage, V 0.1 0.4 V Output Sinking 1.6 mA OL POWER REQUIREMENTS 7 V 3.0 5.25 V DD 8 I (Normal Mode) 0.9 1.25 mA V = VDD, V = GND. Unbuffered Mode DD IH IL 8 I (Normal Mode) 1.1 1.5 mA V = VDD, V = GND. Buffered Mode DD IH IL I (Power-Down) 30 100 A DD 3 Power-Up Time 30 s Exiting Power-Down (Ext. Clock at CLKIN) NOTES 1 Temperature range: K Version, 0C to +85C Y Version, 40C to +105C typical specications are at 25C. 2 See Terminology. 3 Guaranteed by design and characterization, not production tested. 4 Span = Max output frequencyMin output frequency. 5 Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 A in order to overdrive the internal reference. 6 These logic levels apply to CLKOUT only when it is loaded with one CMOS load. 7 Operation at VDD = 2.7 V is also possible with degraded specifications. 8 Outputs unloaded. I increases by C V f when FOUT is loaded. If using a crystal/resonator as the clock source, I will vary depending on the crystal/resonator DD L OUT FOUT DD type (see Clock Generation section). Specications subject to change without notice. 2 REV. C