+2.7 V to +5.5 V, Parallel Input, a Voltage Output 8-Bit DAC AD7801 FUNCTIONAL BLOCK DIAGRAM FEATURES Single 8-Bit DAC 20-Pin SOIC/TSSOP Package +2.7 V to +5.5 V Operation D7 INPUT DAC V I DAC I/V OUT Internal and External Reference Capability REGISTER REGISTER D0 DAC Power-Down Function Parallel Interface POWER-ON MUX RESET WR On-Chip Output Buffer Rail-to-Rail Operation CONTROL LOGIC CS Low Power Operation 1.75 mA max 3.3 V 2 AGND AD7801 Power-Down to 1 mA max 258C REFIN V DGND PD CLR LDAC APPLICATIONS DD Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7801 is a single, 8-bit, voltage out DAC that operates 1. Low Power, Single Supply operation. This part operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output from a single +2.7 V to +5.5 V supply and consumes typically 5 mW at 3 V, making it ideal for battery powered applications. buffer allows the DAC output to swing rail to rail. The AD7801 has a parallel microprocessor and DSP compatible interface with 2. The on-chip output buffer amplifier allows the output of the high speed registers and double buffered interface logic. Data is DAC to swing rail to rail with a settling time of typically 1.2 s. loaded to the input register on the rising edge of CS or WR. 3. Internal or external reference capability. Reference selection for the AD7801 can be either an internal 4. High speed parallel interface. reference derived from the V or an external reference applied DD 5. Power-down capability. When powered down the DAC at the REFIN pin. The output of the DAC can be cleared by consumes less than 1 A at 25C. using the asynchronous CLR input. 6. Packaged in 20-lead SOIC and TSSOP packages. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consump- tion is less than 5 mW at 3.3 V, reducing to less than 3 W in power-down mode. The AD7801 is available in a 20-lead SOIC and a 20-lead TSSOP package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: (V = +2.7 V to +5.5 V, Internal Reference C = 100 pF, R = 10 kV to V and GND. DD L L DD All specifications T to T unless otherwise noted.) AD7801SPECIFICATIONS MIN MAX 1 Parameter B Versions Units Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits 2 Relative Accuracy 1 LSB max Differential Nonlinearity 1 LSB max Guaranteed Monotonic Zero-Code Error +25C 3 LSB typ All Zeros Loaded to DAC Register Full-Scale Error 0.75 LSB typ All Ones Loaded to DAC Register Zero-Code Error Drift 100 V/C typ 3 Gain Error 1 % FSR typ DAC REFERENCE INPUT REFIN Input Range 1 to V /2 V min/V max DD REFIN Input Impedance 10 M typ OUTPUT CHARACTERISTICS Output Voltage Range 0 to V V min/V max DD Output Voltage Settling Time 2 s max Typically 1.2 s Slew Rate 7.5 V/s typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry Digital Feedthrough 0.2 nV-s typ DC Output Impedance 40 typ Short Circuit Current 14 mA typ 4 Power Supply Rejection Ratio 0.0003 %/% max V = 10% DD LOGIC INPUTS Input Current 10 A max V , Input Low Voltage 0.8 V max V = +5 V INL DD V , Input Low Voltage 0.6 V max V = +3 V INL DD V , Input High Voltage 2.4 V min V = +5 V INH DD V , Input High Voltage 2.1 V min V = +3 V INH DD Pin Capacitance 7 pF max POWER REQUIREMENTS 2.7/5.5 V min/V max V DD I (Normal Mode) DAC Active and Excluding Load Current DD = 3.3 V V = V and V = GND V DD IH DD IL 25C 1.55 mA max See Figure 6 to T 1.75 mA max T MIN MAX V = 5.5 V DD 25C 2.35 mA max T to T 2.5 mA max MIN MAX (Power-Down) I DD 25C1 A max V = V and V = GND IH DD IL T to T 2 A max See Figure 18 MIN MAX NOTES 1 Temperature ranges are as follows: B Version: 40C to +105C 2 Relative Accuracy is calculated using a reduced code range of 15 to 245. 3 Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4 Guaranteed by characterization at product release, not production tested. Specifications subject to change without notice. t t 1 2 CS t 3 WR t t 4 5 D7-D0 t t 6 7 LDAC t 8 CLR Figure 1. Timing Diagram for Parallel Data Write REV. 0 2