a +3.3 V to +5 V Quad/Octal 10-Bit DACs AD7804/AD7805/AD7808/AD7809* FUNCTIONAL BLOCK DIAGRAMS FEATURES Four 10-Bit DACs in One Package AV DV AGND DGND DD DD Serial and Parallel Loading Facilities Available V F* OUT POWER ON REFOUT 1.23V REF RESET AD7804/ AD7804 Quad 10-Bit Serial Loading V E* OUT AD7808 REFIN AD7805 Quad 10-Bit Parallel Loading AV DD V BIAS DIVIDER AD7808 Octal 10-Bit Serial Loading MUX V D DAC D OUT COMP AD7809 Octal 10-Bit Parallel Loading CHANNEL D DATA DAC +3.3 V to +5 V Operation CONTROL REG REGISTER REGISTER Power-Down Mode V BIAS Power-On Reset MUX DAC C V C OUT Standby Mode (All DACs/Individual DACs) CHANNEL C DATA DAC Low Power All CMOS Construction CONTROL REG REGISTER REGISTER 10-Bit Resolution V BIAS MUX V B DAC B OUT Double Buffered DAC Registers Dual External Reference Capability CHANNEL B DATA DAC CONTROL REG REGISTER REGISTER APPLICATIONS V Optical Disk Drives BIAS MUX V A DAC A OUT Instrumentation and Communication Systems Process Control and Voltage Setpoint Control PD** CHANNEL A DATA DAC REGISTER REGISTER CONTROL REG Trim Potentiometer Replacement V H* SYSTEM OUT Automatic Calibration CONTROL REG V G* OUT FSIN INPUT SHIFT CLKIN REGISTER & GENERAL DESCRIPTION CONTROL LOGIC SDIN The AD7804/AD7808 are quad/octal 10-bit digital-to-analog **ONLY AD7804 SHOWN FOR CLARITY CLR LDAC **SHOWS ADDITIONAL CHANNELS ON THE AD7808 converters, with serial load capabilities, while the AD7805/AD7809 **PIN ON THE AD7808 ONLY are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3.3 V to +5 V AV DV DD DD AGND DGND ( 10%) power supply and incorporates an on-chip reference. V F* OUT POWER ON REFOUT 1.23V REF RESET AD7805/ V . These DACs provide output signals in the form of V BIAS SWING V E* OUT AD7809 REFIN is derived internally from V . On-chip control registers V SWING BIAS AV DD V BIAS DIVIDER V D include a system control register and channel control registers. MUX DAC D OUT COMP The system control register has control over all DACs in the CHANNEL D DATA DAC package. The channel control registers allow individual control CONTROL REG REGISTER REGISTER of DACs. The complete transfer function of each individual V BIAS V C MUX point using an on-chip DAC C OUT DAC can be shifted around the V BIAS Sub DAC. All DACs contain double buffered data inputs, CHANNEL C DATA DAC REGISTER which allow all analog outputs to be simultaneously updated CONTROL REG REGISTER using the asynchronous LDAC input. V BIAS V B MUX DAC B OUT Control Features Channels Controlled Main DAC Sub DAC DATA DAC CHANNEL B Hardware Clear All REGISTER REGISTER CONTROL REG System Control 1 V BIAS Power Down All V A MUX DAC A OUT 2 System Standby All System Clear All CHANNEL A DATA DAC CONTROL REG REGISTER REGISTER Input Coding All PD** Channel Control SYSTEM CONTROL REG V H* 2 OUT Channel Standby Selective INPUT CS CONTROL REGISTER V G* Channel Clear Selective WR LOGIC OUT V Selective BIAS MODE A0 A1 DB9 DB2 DB1 DB0 A2** CLR LDAC NOTES **ONLY AD7805 SHOWN FOR CLARITY 1 Power-down function powers down all internal circuitry including the reference. **SHOWS ADDITIONAL CHANNELS ON THE AD7809 2 **PIN ON THE AD7809 ONLY Standby functions power down all circuitry except for the reference. *Patent pending. REV. A Index on Page 26. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD7804/AD7805/AD7808/AD7809 AD7804/AD7805SPECIFICATIONS (AV and DV = 3.3 V 6 10% to 5 V 6 10% AGND = DGND = 0 V DD DD Reference = Internal Reference C = 100 pF R = 2 kV to GND. Sub DAC at Midscale. All specifications T to T unless otherwise noted.) L L MIN MAX 1 1 Parameter B Grade C Grade Units Comments STATIC PERFORMANCE MAIN DAC Resolution 10 10 Bits Relative Accuracy 3 3 LSB max Gain Error 3 3 % FSR max 2 Bias Offset Error 80/+40 80/+40 mV max DAC Code = 0.5 Full Scale 3 Zero-Scale Error V V mV max DAC Code = 000H for Offset Binary BIAS BIAS / +40 / +40 16 16 Monotonicity 9 10 Bits and 200H for Twos Complement Coding Minimum Load Resistance 2 2 kW min SUB DAC Resolution 8 8 Bits Differential Nonlinearity 0.125 0.125 LSB typ Refers to an LSB of the Main DAC 0.5 0.5 LSB max OUTPUT CHARACTERISTICS 3 Output Voltage Range V 15/16 V V 15/16 V V Twos Complement Coding BIAS BIAS BIAS BIAS V /16 to 31/16 V V /16 to 31/16 V V Offset Binary Coding BIAS BIAS BIAS BIAS Voltage Output Settling Time to 10 Bits 4 4 m s max Typically 1.5 m s Slew Rate 2.5 2.5 V/m s typ Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around the Major Carry Digital Feedthrough 0.5 0.5 nV-s typ Digital Crosstalk 0.5 0.5 nV-s typ Analog Crosstalk 0.2 0.2 LSB typ DC Output Impedance 2 2 W typ Power Supply Rejection Ratio 0.002 0.002 %/% typ D V 10% DD DAC REFERENCE INPUTS REF IN Range 1.0 to V /2 1.0 to V /2 V min to V max DD DD REF IN Input Leakage 1 1 m A max Typically 1 nA DIGITAL INPUTS Input High Voltage, V V = 5 V 2.4 2.4 V min IH DD Input High Voltage, V V = 3.3 V 2.1 2.1 V min IH DD Input Low Voltage, V V = 5 V 0.8 0.8 V max IL DD Input Low Voltage, V V = 3.3 V 0.6 0.6 V max IL DD Input Leakage Current 10 m A max Input Capacitance 10 10 pF max Input Coding Twos Comp/Binary Twos Comp/Binary REFERENCE OUTPUT REF OUT Output Voltage 1.23 1.23 V nom REF OUT Error 8 8 % max REF OUT Temperature Coefficient 100 100 ppm/ C typ REF OUT Output Impedance 5 5 kW nom POWER REQUIREMENTS V (AV and DV ) 3/5.5 3/5.5 V min to V max DD DD DD I (AI Plus DI ) Excluding Load Currents DD DD DD Normal Mode 12 12 mA max V = V , V = DGND IH DD IL System Standby (SSTBY) Mode 250 250 mAV = V , V = DGND IH DD IL Power-Down (PD) Mode +25 C 0.8 0.8 m A max V = V , V = DGND IH DD IL T T 1.5 1.5 m A max MIN MAX Power Dissipation Excluding Power Dissipated in Load Normal Mode 66 66 mW max System Standby (SSTBY) Mode 1.38 1.38 mW max Power-Down (PD) Mode +25 C 4.4 4.4 m W max T T 8.25 8.25 m W max MIN MAX NOTES 1 Temperature range is 40 C to +85 C. 2 Can be minimized using the Sub DAC. 3 V is the center of the output voltage swing and can be V /2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. BIAS DD Specifications subject to change without notice. 2 REV. A