Clock Recovery and Data Retiming a Phase-Locked Loop AD800/AD802 FUNCTIONAL BLOCK DIAGRAM FEATURES Standard Products C D 44.736 MbpsDS-3 51.84 MbpsSTS-1 155.52 MbpsSTS-3 or STM-1 COMPENSATING LOOP DATA DET ZERO FILTER INPUT Accepts NRZ Data, No Preamble Required Recovered Clock and Retimed Data Outputs VCO Phase-Locked Loop Type Clock RecoveryNo Crystal RECOVERED Required CLOCK f DET OUTPUT Random Jitter: 208 Peak-to-Peak Pattern Jitter: Virtually Eliminated RETIMED RETIMING DATA DEVICE 10KH ECL Compatible OUTPUT Single Supply Operation: 5.2 V or +5 V AD800/AD802 FRAC Wide Operating Temperature Range: 408C to +858C OUTPUT PRODUCT DESCRIPTION During the process of acquisition the frequency detector The AD800 and AD802 employ a second order phase-locked provides a Frequency Acquisition (FRAC) signal which loop architecture to perform clock recovery and data retiming indicates that the device has not yet locked onto the input data. on Non-Return to Zero, NRZ, data. This architecture is This signal is a series of pulses which occur at the points of cycle capable of supporting data rates between 20 Mbps and 160 slip between the input data and the synthesized clock signal. Mbps. The products described here have been defined to work Once the circuit has acquired frequency lock no pulses occur at with standard telecommunications bit rates. 45 Mbps DS-3 and the FRAC output. 52 Mbps STS-1 are supported by the AD800-45 and The inclusion of a precisely trimmed VCO in the device AD800-52 respectively. 155 Mbps STS-3 or STM-1 are eliminates the need for external components for setting center supported by the AD802-155. frequency, and the need for trimming of those components. The Unlike other PLL-based clock recovery circuits, these devices VCO provides a clock output within 20% of the device center do not require a preamble or an external VCXO to lock onto frequency in the absence of input data. input data. The circuit acquires frequency and phase lock using The AD800 and AD802 exhibit virtually no pattern jitter, due two control loops. The frequency acquisition control loop to the performance of the patented phase detector. Total loop initially acquires the clock frequency of the input data. The jitter is 20 peak-to-peak. Jitter bandwidth is dictated by mask phase-lock loop then acquires the phase of the input data, and programmable fractional loop bandwidth. The AD800, used for ensures that the phase of the output signals track changes in the data rates < 90 Mbps, has been designed with a nominal loop phase of the input data. The loop damping of the circuit is bandwidth of 0.1% of the center frequency. The AD802, used dependent on the value of a user selected capacitor this defines for data rates in excess of 90 Mbps, has a loop bandwidth of jitter peaking performance and impacts acquisition time. The 0.08% of center frequency. devices exhibit 0.08 dB jitter peaking, and acquire lock on 5 All of the devices operate with a single +5 V or 5.2 V supply. random or scrambled data within 4 10 bit periods when using a damping factor of 5. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(V = V to V , V = GND, T = T to T , Loop Damping EE MIN MAX CC A MIN MAX AD800/AD802SPECIFICATIONS Factor = 5, unless otherwise noted) AD800-45BQ AD800-52BR AD802-155KR/BR 1 Parameter Condition Min Typ Max Min Typ Max Min Typ Max Units NOMINAL CENTER FREQUENCY 44.736 51.84 155.52 MHz OPERATING TEMPERATURE K Grade 0 70 C RANGE (T to T ) B Grade 40 85 40 85 40 85 C MIN MAX TRACKING RANGE 43 45.5 49 53 155 156 Mbps CAPTURE RANGE 43 45.5 49 53 155 156 Mbps STATIC PHASE ERROR = 1, T = +25C, A V = 5.2 V 2 10 2 10 14 30 Degrees EE = 1 3 11.5 3 11.5 18 37 Degrees RECOVERED CLOCK SKEW t (Figure 1) 0.2 0.6 1 0.2 0.6 1 0.2 0.8 1 ns RCS SETUP TIME t (Figure 1) 2.06 2.37 ns SU TRANSITIONLESS DATA RUN 240 240 240 Bit Periods OUTPUT JITTER = 1 2 2 3.5 Degrees rms 7 2 1 PRN Sequence 2.5 4.7 2.5 4.7 5.4 9.7 Degrees rms 23 2 1 PRN Sequence 2.5 4.7 2.5 4.7 5.4 9.7 Degrees rms JITTER TOLERANCE f = 10 Hz 2,500 2,500 3,000 Unit Intervals f = 2.3 kHz 6.5 Unit Intervals f = 30 kHz 0.47 Unit Intervals f = 1 MHz 0.47 Unit Intervals f = 30 Hz 830 Unit Intervals f = 300 Hz 83 Unit Intervals f = 2 kHz 7.4 Unit Intervals f = 20 kHz 0.47 Unit Intervals f = 6.5 kHz 2.0 7.6 Unit Intervals f = 65 kHz 0.26 0.9 Unit Intervals JITTER TRANSFER Damping Factor Capacitor, C D = 1, Nominal 8.2 6.8 2.2 nF = 5, Nominal 0.22 0.15 0.047 F = 10, Nominal 0.82 0.68 0.22 F Peaking = 1, Nominal T = +25C, V = 5.2 V 2 2 2 dB A EE = 5, Nominal T = +25C, V = 5.2 V 0.08 0.08 0.08 dB A EE = 10, Nominal T = +25C, V = 5.2 V 0.02 0.02 0.02 dB A EE Bandwidth 45 52 130 kHz ACQUISITION TIME 4 4 4 = 1/2 = 1 1 10 1 10 1.5 10 Bit Periods 5 5 5 5 5 5 T = +25C = 5 3 10 8 10 3 10 8 10 4 10 8 10 Bit Periods A 5 5 6 V = 5.2 V = 10 8 10 8 10 1.4 10 Bit Periods EE POWER SUPPLY Voltage (V to V)T = +25C 4.5 5.2 5.5 4.5 5.2 5.5 4.5 5.2 5.5 Volts MIN MAX A Current T = +25C, V = 5.2 V 125 170 125 170 140 180 mA A EE 180 180 205 mA INPUT VOLTAGE LEVELS T = +25C A Input Logic High, V 1.084 0.72 1.084 0.72 1.084 0.72 Volts IH Input Logic Low, V 1.95 1.594 1.95 1.594 1.95 1.594 Volts IH OUTPUT VOLTAGE LEVELS T = +25C A Output Logic High, V 1.084 0.72 1.084 0.72 1.084 0.72 Volts OH Output Logic Low, V 1.95 1.60 1.95 1.60 1.95 1.60 Volts OL INPUT CURRENT LEVELS T = +25C A Input Logic High, I 125 125 125 A IH Input Logic Low, I 80 80 80 A IL OUTPUT SLEW TIMES T = +25C A Rise Time (t ) 20%80% 0.75 1.5 0.75 1.5 0.75 1.5 ns R Fall Time (t ) 80%20% 0.75 1.5 0.75 1.5 0.75 1.5 ns F SYMMETRY = 1/2, T = +25C A Recovered Clock Output V = 5.2 V 45 55 45 55 45 55 % EE NOTES 1 Refer to Glossary for parameter definition. Specifications subject to change without notice. 2 REV. B