Complete 16-Bit CCD/CIS Signal Processor Data Sheet AD80066 FEATURES GENERAL DESCRIPTION 16-bit, 24 MSPS analog-to-digital converter (ADC) The AD80066 is a complete analog signal processor for imaging 4-channel operation up to 24 MHz (6 MHz/channel) applications. It features a 4-channel architecture designed to sample 3-channel operation up to 24 MHz (8 MHz/channel) and condition the outputs of linear charged coupled device (CCD) Selectable input range: 3 V or 1.5 V peak-to-peak or contact image sensor (CIS) arrays. Each channel consists of Input clamp circuitry an input clamp, correlated double sampler (CDS), offset digital- Correlated double sampling to-analog converter (DAC), and programmable gain amplifier 1~6 programmable gain (PGA), multiplexed to a high performance 16-bit ADC. For 300 mV programmable offset maximum flexibility, the AD80066 can be configured as a Internal voltage reference 4-channel, 3-channel, 2-channel, or 1-channel device. Multiplexed byte-wide output The CDS amplifiers can be disabled for use with sensors that Optional single-byte output mode do not require CDS, such as CIS and CMOS sensors. 3-wire serial digital interface The 16-bit digital output is multiplexed into an 8-bit output word, 3 V/5 V digital I/O compatibility which is accessed using two read cycles. There is an optional Power dissipation: 490 mW at 24 MHz operation single-byte output mode. The internal registers are programmed Reduced power mode and sleep mode available through a 3-wire serial interface and enable adjustment of the 28-lead SSOP package gain, offset, and operating mode. The AD80066 operates from a APPLICATIONS 5 V power supply, typically consumes 490 mW of power, and is Flatbed document scanners packaged in a 28-lead SSOP. Film scanners Digital color copiers Multifunction peripherals FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CML AVDD AVSS CAPT CAPB DRVDD DRVSS CDS PGA VINA BAND GAP AD80066 REFERENCE 9-BIT DAC CDS PGA 16 VINB 4:1 8 16-BIT 16:8 DOUT MUX ADC MUX (D 0:7 ) 9-BIT DAC CONFIGURATION CDS PGA VINC REGISTER SCLK DIGITAL SLOAD 9-BIT CONTROL DAC INTERFACE MUX SDATA REGISTER CDS VIND PGA CH. A 6 CH. B 9-BIT CH. C GAIN DAC CH. D REGISTERS CH. A INPUT 9 CH. B OFFSET CLAMP CH. C BIAS OFFSET CH. D REGISTERS CDSCLK1 CDSCLK2 ADCCLK Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. 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Technical Support www.analog.com 08552-001AD80066 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 1-Channel CDS Mode ............................................................... 13 Applications ....................................................................................... 1 1-Channel SHA Mode ............................................................... 13 General Description ......................................................................... 1 Internal Register Map .................................................................... 14 Functional Block Diagram .............................................................. 1 Internal Register Details ................................................................ 15 Revision History ............................................................................... 2 Configuration Register .............................................................. 15 Specifications ..................................................................................... 3 Mux Register ............................................................................... 15 Analog Specifications ................................................................... 3 PGA Gain Registers ................................................................... 15 Digital Specifications ................................................................... 4 Offset Registers ........................................................................... 15 Timing Specifications .................................................................. 5 Circuit Operation ........................................................................... 17 Absolute Maximum Ratings ............................................................ 9 Analog InputsCDS Mode ...................................................... 17 Thermal Resistance ...................................................................... 9 External Input Coupling Capacitors ........................................ 17 ESD Caution .................................................................................. 9 Analog InputsSHA Mode ...................................................... 18 Pin Configuration and Function Descriptions ........................... 10 Programmable Gain Amplifiers (PGA) .................................. 18 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 19 Terminology .................................................................................... 12 Circuit and Layout Recommendations ................................... 19 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 20 4-Channel CDS Mode ................................................................ 13 Ordering Guide .......................................................................... 20 4-Channel SHA Mode................................................................ 13 REVISION HISTORY 4/15Rev. A to Rev. B Changes to Figure 7 .......................................................................... 7 4/10Revision A: Initial Version Rev. B Page 2 of 20