Fiber Optic Receiver with Quantizer and a Clock Recovery and Data Retiming AD807 FEATURES reliance on external components such as a crystal or a SAW Meets CCITT G.958 Requirements filter, to aid frequency acquisition. for STM-1 RegeneratorType A The AD807 acquires frequency and phase lock on input data Meets Bellcore TR-NWT-000253 Requirements for OC-3 using two control loops that work without requiring external Output Jitter: 2.0 Degrees RMS control. The frequency acquisition control loop initially acquires 155 Mbps Clock Recovery and Data Retiming the frequency of the input data, acquiring frequency lock on Accepts NRZ Data, No Preamble Required random or scrambled data without the need for a preamble. At Phase-Locked Loop Type Clock Recovery frequency lock, the frequency error is zero and the frequency No Crystal Required detector has no further effect. The phase acquisition control Quantizer Sensitivity: 2 mV loop then works to ensure that the output phase tracks the input Level Detect Range: 2.0 mV to 30 mV phase. A patented phase detector has virtually eliminated pattern Single Supply Operation: +5 V or 5.2 V jitter throughout the AD807. Low Power: 170 mW The device VCO uses a ring oscillator architecture and patented 10 KH ECL/PECL Compatible Output low noise design techniques. Jitter is 2.0 degrees rms. This low Package: 16-Lead Narrow 150 mil SOIC jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals PRODUCT DESCRIPTION on the IC. The device can withstand hundreds of millivolts of The AD807 provides the receiver functions of data quantization, power supply noise without an effect on jitter performance. signal level detect, clock recovery and data retiming for 155 Mbps The user sets the jitter peaking and acquisition time of the PLL NRZ data. The device, together with a PIN diode/preamplifier by choosing a damping factor capacitor whose value determines combination, can be used for a highly integrated, low cost, low loop damping. CCITT G.958 Type A jitter transfer require- power SONET OC-3 or SDH STM-1 fiber optic receiver. ments can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when Device design guarantees that the clock output frequency will the input signal level has fallen below a user adjustable thresh- drift by less than 20% in the absence of input data transitions. old. The threshold is set with a single external resistor. The Shorting the damping factor capacitor, C , brings the clock D signal level detect circuit 3 dB optical hysteresis prevents chatter output frequency to the VCO center frequency. at the signal level detect output. The AD807 consumes 170 mW and operates from a single The PLL has a factory-trimmed VCO center frequency and a power supply at either +5 V or 5.2 V. frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a FUNCTIONAL BLOCK DIAGRAM CF1 CF2 QUANTIZER PIN + COMPENSATING LOOP DET ZERO FILTER NIN PHASE-LOCKED LOOP VCO SIGNAL THRADJ LEVEL CLKOUTP DETECTOR F DET CLKOUTN LEVEL DETECT DATAOUTP RETIMING COMPARATOR/ + DEVICE DATAOUTN BUFFER AD807 SDOUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD807SPECIFICATIONS (T = T to T , V = V to V , C = 0.1 F, unless otherwise noted.) A MIN MAX CC MIN MAX D Parameter Condition Min Typ Max Unit QUANTIZERDC CHARACTERISTICS Input Voltage Range P or N 2.5 V V IN IN CC 10 Input Sensitivity, V P N , Figure 1, BER = 1 102mV SENSE IN IN 10 Input Overdrive, V Figure 1, BER = 1 10 0.001 2.5 V OD Input Offset Voltage 50 500 V Input Current 510 A 10 Input RMS Noise BER = 1 10 50 V 10 Input Peak-to-Peak Noise BER = 1 10 650 V QUANTIZERAC CHARACTERISTICS Upper 3 dB Bandwidth 180 MHz Input Resistance 1M Input Capacitance 2pF Pulsewidth Distortion 100 ps LEVEL DETECT = INFINITE 0.8 2 4.0 mV Level Detect Range R THRESH R = 49.9 k 4 5 7.4 mV THRESH R = 3.4 k 14 20 25 mV THRESH Response Time DC-Coupled 0.1 1.5 s Hysteresis (Electrical) R = INFINITE 2.3 4.0 10.0 dB THRESH R = 49.9 k 3.0 5.0 9.0 dB THRESH R = 3.4 k 3.0 7.0 10.0 dB THRESH SDOUT Output Logic High Load = +4 mA 3.6 V SDOUT Output Logic Low Load = 1.2 mA 0.4 V PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY 155.52 MHz CAPTURE RANGE 155 156 MHz TRACKING RANGE 155 156 MHz 7 STATIC PHASE ERROR 2 1 PRN Sequence 4 20 Degrees SETUP TIME (t ) Figure 2 3.0 3.2 3.5 ns SU HOLD TIME (t ) Figure 2 3.0 3.1 3.3 ns H PHASE DRIFT 240 Bits, No Transitions 40 Degrees 7 JITTER 2 1 PRN Sequence 2.0 Degrees RMS 23 2 1 PRN Sequence 2.0 2.7 Degrees RMS JITTER TOLERANCE f = 10 Hz 3000 Unit Intervals f = 6.5 kHz 4.5 7.6 Unit Intervals f = 65 kHz 0.45 1.0 Unit Intervals f = 1.3 MHz 0.45 0.67 Unit Intervals JITTER TRANSFER Peaking (Figure 11) C = 0.15 F 0.08 dB D C = 0.33 F 0.04 dB D Bandwidth 65 92 130 kHz Acquisition Time 23 5 6 C = 0.1 F2 1 PRN Sequence, T = 25C4 10 2 10 Bit Periods D A 6 C = 0.33 FV = 5 V, V = GND 2 10 Bit Periods D CC EE POWER SUPPLY VOLTAGE V to V 4.5 5.5 Volts MIN MAX POWER SUPPLY CURRENT V = 5.0 V, V = GND, T = 25C 25 34.5 39.5 mA CC EE A PECL OUTPUT VOLTAGE LEVELS Output Logic High, V V = 5.0 V, V = GND, T = 25C 1.2 1.0 0.7 Volts OH CC EE A Output Logic Low, V Referenced to V 2.0 1.8 1.7 Volts OL CC SYMMETRY (Duty Cycle) = 1/2, T = 25C, A Recovered Clock Output, Pin 5 V = 5 V, V = GND 50.1 54.1 % CC EE OUTPUT RISE / FALL TIMES Rise Time (t ) 20%80% 1.1 1.5 ns R Fall Time (t ) 80%20% 1.1 1.5 ns F Specifications subject to change without notice. 2 REV. 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