Fiber Optic Receiver with Quantizer and a Clock Recovery and Data Retiming AD808 FEATURES frequency acquisition without false lock. This eliminates a reli- Meets CCITT G.958 Requirements ance on external components such as a crystal or a SAW filter, for STM-4 RegeneratorType A to aid frequency acquisition. Meets Bellcore TR-NWT-000253 Requirements for OC-12 The AD808 acquires frequency and phase lock on input data Output Jitter: 2.5 Degrees RMS using two control loops that work without requiring external 622 Mbps Clock Recovery and Data Retiming control. The frequency acquisition control loop initially acquires Accepts NRZ Data, No Preamble Required the frequency of the input data, acquiring frequency lock on Phase-Locked Loop Type Clock Recovery random or scrambled data without the need for a preamble. At No Crystal Required frequency lock, the frequency error is zero and the frequency Quantizer Sensitivity: 4 mV detector has no further effect. The phase acquisition control Level Detect Range: 10 mV to 40 mV, Programmable loop then works to ensure that the output phase tracks the input Single Supply Operation: +5 V or 5.2 V phase. A patented phase detector has virtually eliminated pat- Low Power: 400 mW tern jitter throughout the AD808. 10 KH ECL/PECL Compatible Output The device VCO uses a ring oscillator architecture and patented Package: 16-Lead Narrow 150 mil SOIC low noise design techniques. Jitter is 2.5 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically PRODUCT DESCRIPTION isolated process that provides immunity from extraneous signals The AD808 provides the receiver functions of data quantiza- on the IC. The device can withstand hundreds of millivolts of tion, signal level detect, clock recovery and data retiming for power supply noise without an effect on jitter performance. 622 Mbps NRZ data. The device, together with a PIN The user sets the jitter peaking and acquisition time of the PLL diode/preamplifier combination, can be used for a highly inte- by choosing a damping factor capacitor whose value determines grated, low cost, low power SONET OC-12 or SDH STM-4 loop damping. CCITT G.958 Type A jitter transfer require- fiber optic receiver. ments can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when Device design guarantees that the clock output frequency will the input signal level has fallen below a user adjustable thresh- drift by less than 20% in the absence of input data transitions. old. The threshold is set with a single external resistor. The Shorting the damping factor capacitor, C , brings the clock D signal level detect circuit 3 dB optical hysteresis prevents chatter output frequency to the VCO center frequency. at the signal level detect output. The AD808 consumes 400 mW and operates from a single The PLL has a factory trimmed VCO center frequency and a power supply at either +5 V or 5.2 V. frequency acquisition control loop that combine to guarantee FUNCTIONAL BLOCK DIAGRAM CF1 CF2 QUANTIZER PIN COMPENSATING LOOP F DET S ZERO FILTER NIN PHASE-LOCKED LOOP VCO SIGNAL THRADJ LEVEL CLKOUTP F DETECTOR DET CLKOUTN LEVEL DATAOUTP RETIMING DETECT DEVICE DATAOUTN COMPARATOR/ BUFFER AD808 SDOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD808SPECIFICATIONS (T = T to T , V = V to V , C = 0.47 mF, unless otherwise noted) A MIN MAX S MIN MAX D Parameter Condition Min Typ Max Units QUANTIZERDC CHARACTERISTICS or N 2.5 V V Input Voltage Range P IN IN S 10 Input Sensitivity, V P N , Figure 1, BER = 1 10 10 4.0 mV SENSE IN IN 10 Figure 1, BER = 1 10 5 2.0 mV Input Overdrive, V OD Input Offset Voltage 1.0 mV Input Current 10 A 10 Input RMS Noise BER = 1 10 100 V 10 Input Peak-to-Peak Noise BER = 1 10 1.5 mV QUANTIZERAC CHARACTERISTICS Upper 3 dB Bandwidth 600 800 MHz Input Resistance 10 k Input Capacitance 2pF Pulsewidth Distortion 50 ps LEVEL DETECT Level Detect Range R = 22.1 k 6.5 10 13.5 mV THRESH = 6.98 k 13 18 23 mV R THRESH R = 0 28.5 40 45.5 mV THRESH Response Time DC Coupled 0.1 1.5 s Hysteresis (Electrical) R = 22.1 k (See Figure 8) 5 9.0 dB THRESH = 6.98 k 3.0 5.1 9.0 dB R THRESH R = 0 3.0 7.0 10.0 dB THRESH SDOUT Output Logic High Load = +3.2 mA 4.0 4.7 V SDOUT Output Logic Low Load = 3.2 mA 0.2 0.4 V PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY 622.08 MHz CAPTURE RANGE 620 624 MHz TRACKING RANGE 620 624 MHz 7 STATIC PHASE ERROR (See Figure 7) 2 1 PRN Sequence 22 81 Degrees SETUP TIME (t ) Figure 2 550 900 ps SU HOLD TIME (t ) Figure 2 700 1050 ps H PHASE DRIFT 240 Bits, No Transitions 50 Degrees 7 JITTER 2 1 PRN Sequence 2.5 3.6 Degrees rms 23 2 1 PRN Sequence 2.5 3.6 Degrees rms JITTER TOLERANCE f = 30 Hz 3000 Unit Intervals f = 300 Hz 24 300 Unit Intervals f = 25 kHz 1.7 3.7 Unit Intervals f = 250 kHz 0.28 0.56 Unit Intervals f = 5 MHz 0.18 0.45 Unit Intervals JITTER TRANSFER = 0.47 F 0.04 dB Peaking (Figure 14) C D Bandwidth 333 450 kHz Acquisition Time 23 6 6 C = 0.1 F2 1 PRN Sequence, T = +25C2 10 3 10 Bit Periods D A 6 6 C = 0.47 FV = 5 V, V = GND 8 10 12 10 Bit Periods D CC EE POWER SUPPLY VOLTAGE V to V 4.5 5.5 Volts MIN MAX POWER SUPPLY CURRENT V = 5.0 V, V = GND, CC EE T = +25C 55 80 100 mA A PECL OUTPUT VOLTAGE LEVELS Output Logic High, V T = +25C 1.2 1.0 0.7 Volts OH A Output Logic Low, V Referenced to V 2.2 2.0 1.7 Volts OL CC SYMMETRY (Duty Cycle) = 1/2, T = +25C, A Recovered Clock Output, Pin 5 V = 5 V, V = GND 45 55 % CC EE OUTPUT RISE / FALL TIMES ) 20%80% 174 350 500 ps Rise Time (t R Fall Time (t ) 80%20% 136 315 500 ps F CLOCK SKEW (t ) Positive Number Indicates Clock RCS Leading Data 100 130 250 ps Specifications subject to change without notice. 2 REV. 0