Ultralow Distortion, High Speed, 0.95 nV/Hz Voltage Noise Op Amp Data Sheet AD8099 FEATURES CONNECTION DIAGRAMS AD8099 Ultralow noise: 0.95 nV/Hz, 2.6 pA/Hz TOP VIEW (Not to Scale) Ultralow distortion nd 2 harmonic R = 1 k , G = +2 L DISABLE 1 8 +V S 92 dB at 10 MHz 7 V FEEDDBACK 2 OUT rd 3 harmonic R = 1 k , G = +2 L 6 C IN 3 C 105 dB at 10 MHz 5 V +IN 4 S High speed NOTES 1. SOLDER THE EXPOSED PADDLE Gain bandwidth product (GBWP): 3.8 GHz TO THE GROUND PLANE. 3 dB bandwidth Figure 1. 8-Lead LFCSP (CP-8-13) 700 MHz (G = +2) AD8099 550 MHz (G = +10) TOP VIEW (Not to Scale) Slew rate 475 V/s (G = +2) FEEDBACK 1 8 DISABLE IN 2 7 +V 1350 V/s (G = +10) S +IN 3 6 V OUT New pinout V 4 5 C S C Custom external compensation, gain range 1, +2 to +10 NOTES Supply current: 15 mA 1. SOLDER THE EXPOSED PADDLE TO THE GROUND PLANE. Offset voltage: 0.5 mV max Figure 2. 8-Lead SOIC-EP (RD-8-1) Wide supply voltage range: 5 V to 12 V The AD8099 drives 100 loads at breakthrough performance APPLICATIONS levels with only 15 mA of supply current. With the wide supply Preamplifiers voltage range (5 V to 12 V), low offset voltage (0.1 mV typ), wide Receivers bandwidth (700 MHz for G = +2), and a GBWP up to 3.8 GHz, Instrumentation the AD8099 is designed to work in a wide variety of applications. Filters The AD8099 is available in a 3 mm 3 mm lead frame chip scale Intermediate frequency (IF) and baseband amplifiers package (LFCSP) with a new pinout that is specifically optimized Analog-to-digital drivers for high performance, high speed amplifiers. The new LFCSP and Digital-to-analog converter (DAC) buffers pinout enable the breakthrough performance that previously was Optical electronics not achievable with amplifiers. The AD8099 is rated to work GENERAL DESCRIPTION over the extended industrial temperature range, 40C to +125C. 40 The AD8099 is an ultralow noise (0.95 nV/Hz) and distortion G = +2 V = 2V p-p OUT (92 dBc at 10 MHz) voltage feedback op amp, the combination 50 V = 5V S R = 1k of which makes it ideal for 16- and 18-bit systems. The AD8099 L 60 features a new, highly linear, low noise input stage that increases 70 the full power bandwidth (FPBW) at low gains with high slew rates. The Analog Devices, Inc., proprietary next generation 80 extra fast complimentary bipolar (XFCB) process enables such 90 high performance amplifiers with relatively low power. 100 The AD8099 features external compensation, which lets the user 110 set the gain bandwidth product. External compensation allows 120 gains from +2 to +10 with minimal trade-off in bandwidth. The SOLID LINE SECOND HARMONIC AD8099 also features an extremely high slew rate of 1350 V/s, DOTTED LINE THIRD HARMONIC 130 0.1 1.0 10.0 giving the designer flexibility to use the entire dynamic range FREQUENCY (MHz) without trading off bandwidth or distortion. The AD8099 Figure 3. Harmonic Distortion vs. Frequency and Gain (SOIC) settles to 0.1% in 18 ns and recovers from overdrive in 50 ns. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com HARMONIC DISTORTION (dBc) 04511-0-002 04511-0-001 04511-A-013AD8099 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Using the AD8099 ...................................................................... 16 Applications ....................................................................................... 1 Circuit Components .................................................................. 16 General Description ......................................................................... 1 Recommended Values ............................................................... 17 Connection Diagrams ...................................................................... 1 Circuit Configurations .............................................................. 17 Revision History ............................................................................... 2 Performance vs. Component Values ........................................ 19 Specifications ..................................................................................... 3 Total Output Noise Calculations and Design ......................... 21 Specifications with 5 V Supply ................................................. 3 Input Bias Current and DC Offset ........................................... 21 Specifications with +5 V Supply ................................................. 4 DISABLE Pin and Input Bias Cancellation ............................. 21 Absolute Maximum Ratings ............................................................ 5 16-Bit ADC Driver ..................................................................... 22 Maximum Power Dissipation ..................................................... 5 Circuit Considerations .............................................................. 23 ESD Caution .................................................................................. 5 Design Tools and Technical Support ....................................... 23 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 24 Applications Information .............................................................. 16 REVISION HISTORY 7/2016Rev. D to Rev. E 6/2004Rev. A to Rev. B Changed CP-8-2 to CP-8-13 ........................................ Throughout Change to General Description Section ......................................... 1 Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Maximum Power Dissipation Section ........................ 5 Changes to Figure 67 ...................................................................... 19 Changes to Applications Section ................................................. 16 Added Figure 68 to Figure 70 Renumbered Sequentially ........ 19 Changes to Table 7 .......................................................................... 24 Changes to Figure 71 ...................................................................... 20 Changes to Ordering Guide .......................................................... 26 Added Figure 72 and Figure 73..................................................... 20 1/2004Rev. 0 to Rev. A Changes to PCB Layout Section ................................................... 23 Updated Outline Dimensions ....................................................... 24 Inserted Figure 3 ................................................................................ 1 Changes to Ordering Guide ......................................................... 24 Changes to Specifications Section ................................................... 3 Inserted Figure 22 to Figure 34 ........................................................ 8 8/2013Rev. C to Rev. D Inserted Figure 51 to Figure 55 ..................................................... 14 Changes to Figure 42 Caption ....................................................... 12 Changes to Theory of Operation Section.................................... 16 Changes to Figure 49 ...................................................................... 13 Changes to Circuit Components Section .................................... 17 Changes to Ordering Guide .......................................................... 25 Changes to Table 4 .......................................................................... 18 Changes to Figure 60 ...................................................................... 18 1/2013Rev. B to Rev. C Changes to Total Output Noise Calculations and Added EPAD Note to Figure 1 and Figure 2 ................................. 1 Design Section ................................................................................ 21 Changes to PCB Layout Section and Design Tools and Changes to Figure 60 ...................................................................... 22 Technical Support Section ............................................................. 23 Changes to Figure 62 ...................................................................... 23 Deleted Figure 72, Figure 73, Evaluation Boards Section, Changes to 16-Bit ADC Driver Section ...................................... 23 and Table 7 ....................................................................................... 24 Changes to Table 6 .......................................................................... 23 Updated Outline Dimensions ....................................................... 25 Additions to PCB Layout Section ................................................. 23 Changes to Ordering Guide .......................................................... 26 11/2003Revision 0: Initial Version Rev. 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