Triple Differential Receiver with 300 Meter Adjustable Line Equalization Data Sheet AD8122 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V V PEAK FILTER OFFSET GAIN Compensates cables up to 300 meters for wideband video 60 MHz equalized BW at 300 meters of UTP cable COAX/UTP 120 MHz equalized BW at 150 meters of UTP cable Fast time domain performance IN R OUT R 70 ns settling time to 1% at 300 meters of UTP cable +IN R 7 ns rise/fall times with 2 V step at 300 meters of UTP cable GAIN R 3 frequency response gain adjustment pins IN G OUT G High frequency peaking adjustment (V ) +IN PEAK G Output low-pass filter cutoff adjustment (V ) GAIN FILTER G IN B Broadband flat gain adjustment (V ) GAIN OUT B Selectable for UTP or coaxial compensation +IN B DC output offset adjustment pin (V ) GAIN B OFFSET IN CMP1 Low output offset voltage: 4 mV at G = 1 OUT CMP1 +IN Compensates both RGB and YPbPr CMP1 2 on-chip comparators with hysteresis can be used IN CMP2 OUT for common-mode sync pulse extraction CMP2 +IN CMP2 AD8122 Available in 40-lead, 6 mm 6 mm LFCSP Figure 1. APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video GENERAL DESCRIPTION The AD8122 is a high speed, triple differential receiver and The selection of UTP or coaxial cable compensation responses equalizer that compensates for the transmission losses of UTP is determined by the binary COAX/UTP input, which can be cables up to 300 meters in length and coaxial cables up to left floating in UTP applications. The V input allows the OFFSET 200 meters in length. Various gain stages are summed to best dc voltage at the output to be adjusted, which can be useful in approximate the inverse frequency response of the cable. Each dc-coupled systems. channel features a high impedance differential input with high For added flexibility, the gain of each channel can be set to 1 rejection of common-mode (CM) signals that is ideal for inter- or 2 using the associated gain control pin. facing directly with the cable. The AD8122 is available in a 6 mm 6 mm, 40-lead LFCSP The AD8122 has two control inputs for optimal cable and is rated to operate over the extended temperature range compensation, one LPF control input, an input to select UTP or of 40C to +85C. coaxial cable, and an input to adjust the dc output offset. The cable compensation inputs are used to compensate for different cable lengths: the V input controls the amount of high frequency PEAK peaking, and the V input adjusts the broadband flat gain to GAIN compensate for the flat cable loss. The V input controls the FILTER cutoff frequency of output low-pass filters on each channel. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2012 Analog Devices, Inc. All rights reserved. 10780-001AD8122 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 On-Chip Comparators .............................................................. 12 Applications ....................................................................................... 1 Input Single-Ended Voltage Range Considerations .............. 12 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 13 General Description ......................................................................... 1 Basic Operation .......................................................................... 13 Revision History ............................................................................... 2 Input Overdrive Recovery and Protection .............................. 13 Specifications ..................................................................................... 3 Comparator Applications .......................................................... 13 Absolute Maximum Ratings ............................................................ 5 Sync Pulse Extraction Using Comparators ............................. 14 Thermal Resistance ...................................................................... 5 Using the V , V , V , and V Inputs ................. 15 PEAK GAIN FILTER OFFSET Maximum Power Dissipation ..................................................... 5 Using the COAX/UTP Selector ................................................ 15 ESD Caution .................................................................................. 5 Driving High Impedance Capacitive Loads ........................... 15 Pin Configuration and Function Descriptions ............................. 6 Driving 75 Cable with the AD8122 ..................................... 15 Typical Performance Characteristics ............................................. 8 Layout and Power Supply Decoupling Considerations ......... 15 Theory of Operation ...................................................................... 12 Input Common-Mode Range ................................................... 15 Adjustable Control Voltages ...................................................... 12 Power-Down ............................................................................... 16 Differential Inputs ...................................................................... 12 Outline Dimensions ....................................................................... 17 Outputs ........................................................................................ 12 Ordering Guide .......................................................................... 17 REVISION HISTORY 7/12Revision 0: Initial Version Rev. 0 Page 2 of 20