Triple Differential Driver with Output Pull-Down Data Sheet AD8133 FEATURES FUNCTIONAL BLOCK DIAGRAM Triple high speed fully differential driver 225 MHz 3 dB large signal bandwidth 24 23 22 21 20 19 Easily drives 1.4 V p-p video signal into source-terminated OPD 1 18 V C 100 UTP cable OCM AD8133 1600 V/s slew rate V 2 17 V S S+ Fixed internal gain of 2 IN A 3 16 IN C Internal common-mode feedback network +IN A 4 15 +IN C Output balance error 60 dB 50 MHz B V 5 14 V S A C S Differential input and output OUT A 6 13 OUT C Differential-to-differential or single-ended-to-differential 7 8 9 10 11 12 operation Adjustable output common-mode voltage Output pull-down feature for line isolation Figure 1. Low distortion: 64 dB SFDR 10 MHz on 5 V supply, R = 200 L, dm 0 Low offset: 4 mV typical output referred on 5 V supply V = 2V p-p OUT, dm 10 V /V OUT, cm OUT, dm Low power: 26 mA 5 V for three drivers 20 Wide supply voltage range: +5 V to 5 V V = 5V S Available in space-saving packaging: 4 mm 4 mm LFCSP 30 40 APPLICATIONS 50 V = +5V S KVM (keyboard-video-mouse) networking 60 UTP (unshielded twisted pair) driving 70 Differential signal multiplexing 80 90 GENERAL DESCRIPTION 100 The AD8133 is a major advancement beyond using discrete 1 10 100 500 FREQUENCY (MHz) op amps for driving differential RGB signals over twisted pair Figure 2. Output Balance vs. Frequency cable. The AD8133 is a triple, low cost differential or single- Manufactured on Analog Devices next generation XFCB ended input to differential output driver, and each amplifier has bipolar process, the AD8133 has a large signal bandwidth of a fixed gain of 2 to compensate for the attenuation of line 225 MHz and a slew rate of 1600 V/s. The AD8133 has an termination resistors. The AD8133 is specifically designed for RGB internal common-mode feedback feature that provides output signals but can be used for any type of analog signals or high speed amplitude and phase matching that is balanced to 60 dB at data transmission. The AD8133 is capable of driving either 50 MHz, suppressing harmonics and minimizing radiated Category 5 unshielded twisted pair (UTP) cable or differential electromagnetic interference (EMI). printed circuit board transmission lines with minimal signal degradation. The output common-mode level is easily adjustable by applying a voltage to the VOCM input pin. The VOCM input can also be used The outputs of the AD8133 can be set to a low voltage state to to transmit signals on the output common-mode voltages. be used with series diodes for line isolation, allowing easy differential multiplexing over the same twisted pair cable. The The AD8133 is available in a 24-lead LFCSP package and can AD8133 driver can be used in conjunction with the AD8129 operate over the temperature range of 40C to +85C. and AD8130 differential receivers. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com OUTPUT BALANCE ERROR (dB) +OUT A V S+ V IN B S+ +OUT B +IN B OUT B V S V V A S+ OCM +OUT C V B OCM 04769-0-001 04769-0-034AD8133 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Calculating an Application Circuits Input Impedance ......... 14 Applications ....................................................................................... 1 Input Common-Mode Voltage Range in Single-Supply Applications .................................................................................. 14 General Description ......................................................................... 1 Driving a Capacitive Load ......................................................... 14 Functional Block Diagram .............................................................. 1 Output Pull-Down (OPD) ........................................................ 14 Revision History ............................................................................... 2 Output Common-Mode Control ............................................. 14 Specifications ..................................................................................... 3 Applications ..................................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Driving RGB Video Signals Over Category-5 UTP Cable.... 15 Thermal Resistance ...................................................................... 5 Output Pull-Down ..................................................................... 16 ESD Caution .................................................................................. 5 KVM Networks ........................................................................... 16 Pin Configuration and Function Descriptions ............................. 6 Layout and Power Supply Decoupling Considerations .... 16 Typical Performance Characteristics ............................................. 7 Amplifier-to-Amplifier Isolation ............................................. 16 Test Circuit ...................................................................................... 12 Exposed Paddle (EP).................................................................. 16 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 17 Definition of Terms .................................................................... 13 Ordering Guide .......................................................................... 17 Analyzing an Application Circuit ............................................. 13 Closed-Loop Gain ...................................................................... 13 REVISION HISTORY 3/16Rev. 0 to Rev. A Changed CP-24 to CP-24-10 ............................................. Universal Changes to Figure 4 and Table 5 ..................................................... 6 Added Test Circuit Section ............................................................ 12 Moved Figure 33 Renumbered Sequentially .............................. 12 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 7/04Revision 0: Initial Version Rev. A Page 2 of 17