AD8138ARMZ-REEL7 Analog Devices

Low Distortion, Differential ADC Driver Data Sheet AD8138 FEATURES PIN CONFIGURATION Easy to use, single-ended-to-differential conversion IN 1 8 +IN Adjustable output common-mode voltage V 2 7 NC OCM Externally adjustable gain V+ 3 6 V +OUT 4 5 OUT Low harmonic distortion AD8138 94 dBc SFDR at 5 MHz NC = NO CONNECT 85 dBc SFDR at 20 MHz Figure 1. 3 dB bandwidth of 320 MHz, G = +1 TYPICAL APPLICATION CIRCUIT Fast settling to 0.01% of 16 ns 5V Slew rate 1150 V/s 5V Fast overdrive recovery of 4 ns 499 Low input voltage noise of 5 nV/Hz 499 V AVDD DVDD + IN AIN 1 mV typical offset voltage V OCM DIGITAL ADC AD8138 OUTPUTS Wide supply range +3 V to 5 V 499 AIN V AVSS REF Low power 90 mW on 5 V 0.1 dB gain flatness to 40 MHz 499 Available in 8-Lead SOIC and MSOP packages Figure 2. APPLICATIONS ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers GENERAL DESCRIPTION The AD8138 is a major advancement over op amps for The AD8138 eliminates the need for a transformer with high differential signal processing. The AD8138 can be used as a performance ADCs, preserving the low frequency and dc infor- single-ended-to-differential amplifier or as a differential-to- mation. The common-mode level of the differential output is differential amplifier. The AD8138 is as easy to use as an op adjustable by a voltage on the VOCM pin, easily level-shifting the amp and greatly simplifies differential signal amplification and input signals for driving single-supply ADCs. Fast overload driving. Manufactured on the proprietary ADI XFCB bipolar recovery preserves sampling accuracy. process, the AD8138 has a 3 dB bandwidth of 320 MHz and The AD8138 distortion performance makes it an ideal ADC delivers a differential signal with the lowest harmonic distortion driver for communication systems, with distortion performance available in a differential amplifier. The AD8138 has a unique good enough to drive state-of-the-art 10-bit to 16-bit converters internal feedback feature that provides balanced output gain at high frequencies. The high bandwidth and IP3 of the and phase matching, suppressing even order harmonics. The AD8138 also make it appropriate for use as a gain block in IF internal feedback circuit also minimizes any gain error that and baseband signal chains. The AD8138 offset and dynamic would be associated with the mismatches in the external gain performance makes it well suited for a wide variety of signal setting resistors. processing and data acquisition applications. The differential output of the AD8138 helps balance the input The AD8138 is available in both SOIC and MSOP packages for to differential ADCs, maximizing the performance of the ADC. operation over 40C to +85C temperatures. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 19992016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 01073-001 01073-002AD8138 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Definition of Terms .................................................................... 16 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 17 Pin Configuration ............................................................................. 1 Analyzing an Application Circuit ............................................ 17 Typical Application Circuit ............................................................. 1 Setting the Closed-Loop Gain .................................................. 17 General Description ......................................................................... 1 Estimating the Output Noise Voltage ...................................... 17 Revision History ............................................................................... 2 The Impact of Mismatches in the Feedback Networks ......... 18 Specif icat ions ..................................................................................... 3 Calculating the Input Impedance of an Application ............. 18 D to OUT Specifications ...................................................... 3 Input Common-Mode Voltage Range in Single-Supply IN Applications ................................................................................ 18 VOCM to OUT Specifications ..................................................... 4 Setting the Output Common-Mode Voltage .......................... 18 DIN to OUT Specifications ...................................................... 5 Driving a Capacitive Load ......................................................... 18 VOCM to OUT Specifications ..................................................... 6 Layout, Grounding, and Bypassing .............................................. 19 Absolute Maximum Ratings ............................................................ 7 Balanced Transformer Driver ....................................................... 20 Thermal Resistance ...................................................................... 7 High Performance ADC Driving ................................................. 21 ESD Caution .................................................................................. 7 3 V Operation ................................................................................. 22 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 23 Test Circuits ..................................................................................... 15 Operational Description ................................................................ 16 REVISION HISTORY Added New Paragraph after Table I ............................................. 10 3/16Rev. F to Rev. G Updated Outline Dimensions ....................................................... 14 Changes to Setting the Closed-Loop Gain Section .................... 17 Changes to Figure 46 ...................................................................... 21 7/02Rev. C to Rev. D Changes to Figure 47 ...................................................................... 22 Addition of TPC 35 and TPC 36 ..................................................... 8 1/06Rev. E to Rev. F 6/01Rev. B to Rev. C Changes to Features .......................................................................... 1 Edits to Specifications ...................................................................... 2 Added Thermal Resistance Section and Maximum Power Edits to Ordering Guide ................................................................... 4 Dissipation Section ........................................................................... 7 Changes to Balanced Transformer Driver Section ..................... 20 12/00Rev. A to Rev. B Changes to Ordering Guide .......................................................... 23 9/99Rev. 0 to Rev. A 3/03Rev. D to Rev. E Changes to Specifications ................................................................ 2 3/99Rev. 0: Initial Version Changes to Ordering Guide ............................................................ 4 Changes to TPC 16 ........................................................................... 6 Changes to Table I ............................................................................ 9 Rev. G Page 2 of 24