Low Noise, Rail-to-Rail, Differential ADC Driver Data Sheet AD8139 FEATURES FUNCTIONAL BLOCK DIAGRAMS AD8139 Fully differential IN 1 8 +IN Low noise V 2 7 NIC OCM 2.25 nV/Hz V+ 3 6 V 2.1 pA/Hz +OUT 4 5 OUT Low harmonic distortion NIC = NO INTERNAL CONNECTION. 98 dBc SFDR at 1 MHz Figure 1. 8-Lead SOIC 85 dBc SFDR at 5 MHz AD8139 72 dBc SFDR at 20 MHz TOP VIEW High speed (Not to Scale) 410 MHz, 3 dB BW (G = 1) IN 1 8 +IN 800 V/s slew rate V 2 7 NIC OCM 45 ns settling time to 0.01% V V+ 3 6 69 dB output balance at 1 MHz 5 OUT +OUT 4 80 dB dc CMRR NIC = NO INTERNAL CONNECTION. Low offset: 0.5 mV maximum Figure 2. 8-Lead LFCSP Low input offset current: 0.5 A maximum Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Wide supply voltage range: 5 V to 12 V Available in a small SOIC package and an 8-lead LFCSP The AD8139 is manufactured on the proprietary Analog Devices, APPLICATIONS Inc., second-generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only 2.25 nV/Hz. ADC drivers to 18 bits Single-ended-to-differential converters The AD8139 is available in an 8-lead SOIC package with an Differential filters exposed paddle (EP) on the underside of its body and a 3 mm Level shifters 3 mm LFCSP. It is rated to operate over the temperature range Differential PCB drivers of 40C to +125C. Differential cable drivers 100 GENERAL DESCRIPTION The AD8139 is an ultralow noise, high performance differential amplifier with rail-to-rail output. With its low noise, high SFDR, and wide bandwidth, it is an ideal choice for driving analog-to-digital converters (ADCs) with resolutions to 18 bits. 10 The AD8139 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order harmonic distortion products. Fully differential and single-ended-to-differential gain configurations 1 10 100 1k 10k 100k 1M 10M 100M 1G are easily realized by the AD8139. Simple external feedback FREQUENCY (Hz) networks consisting of four resistors determine the closed-loop Figure 3. Input Voltage Noise vs. Frequency gain of the amplifier. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INPUT VOLTAGE NOISE (nV/ Hz) 04679-102 04679-001 04679-078AD8139 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................9 General Description ......................................................................... 1 Test Circuits ..................................................................................... 18 Functional Block Diagrams ............................................................. 1 Theory of Operation ...................................................................... 19 Revision History ............................................................................... 2 Typical Connection and Definition of Terms ........................ 19 Specifications ..................................................................................... 3 Applications Information .............................................................. 20 V = 5 V, V = 0 V .................................................................. 3 Estimating Noise, Gain, and Bandwidth with Matched S OCM Feedback Networks .................................................................... 20 V = 5 V, V = 2.5 V ................................................................. 5 S OCM Outline Dimensions ....................................................................... 25 Absolute Maximum Ratings ............................................................ 7 Ordering Guide .......................................................................... 26 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 REVISION HISTORY 6/2016Rev. B to Rev. C 8/2004Rev. 0 to Rev. A Changed CP-8-2 to CP-8-13 ........................................ Throughout Added 8-Lead LFCSP ......................................................... Universal Changes to Figure 1 and Figure 2 ................................................... 1 Changes to General Description Section ....................................... 1 Changes to Figure 5, Figure 6, and Table 5 ................................... 8 Changes to Figure 2 ........................................................................... 1 Updated Outline Dimensions ....................................................... 25 Changes to V = 5 V, V = 0 V Specifications ......................... 3 S OCM Changes to Ordering Guide ......................................................... 26 Changes to V = 5 V, V = 2.5 V Specifications ......................... 5 S OCM Changes to Table 4 ............................................................................. 7 10/2007Rev. A to Rev. B Changes to Maximum Power Dissipation Section ........................ 7 Changes to General Description Section ...................................... 1 Changes to Figure 26 and Figure 29............................................. 12 Added Figure 2 Renumbered Sequentially .................................. 1 Added Figure 39 and Figure 42 Renumbered Sequentially ..... 14 Changes to Table 1 ............................................................................ 3 Changes to Figure 45 to Figure 47 ................................................ 15 Changes to Table 2 ............................................................................ 5 Added Figure 48 ............................................................................. 15 Changes to Table 6 and Layout ....................................................... 8 Changes to Figure 52 and Figure 53............................................. 16 Added Figure 6 .................................................................................. 8 Changes to Figure 55 and Figure 56............................................. 17 Changes to Figure 30 ...................................................................... 12 Changes to Table 6 .......................................................................... 19 Changes to Layout .......................................................................... 17 Changes to Voltage Gain Section ................................................. 19 Changes to Figure 63 ...................................................................... 22 Changes to Driving a Capacitive Load Section .......................... 22 Changes to Exposed Paddle (EP) Section ................................... 23 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 Updated Outline Dimensions ....................................................... 24 5/2004Revision 0: Initial Version Rev. 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