Single-Lead, Heart Rate Monitor Front End Data Sheet AD8232 FEATURES FUNCTIONAL BLOCK DIAGRAM 20 19 18 17 16 Fully integrated single-lead ECG front end HPSENSE IAOUT REFIN +V GND S Low supply current: 170 A (typical) HPDRIVE 1 FR 15 Common-mode rejection ratio: 80 dB (dc to 60 Hz) S1 10k A3 +IN Two or three electrode configurations 2 High signal gain (G = 100) with dc blocking capabilities AC/DC 14 IA IN 3 2-pole adjustable high-pass filter Accepts up to 300 mV of half cell potential SDN 13 150k AD8232 Fast restore feature improves filter settling 4 LOD+ Uncommitted op amp RLDFB C1 12 3-pole adjustable low-pass filter with adjustable gain LEADS-OFF 5 A2 DETECTION Leads off detection: ac or dc options LOD RLD 11 C2 Integrated right leg drive (RLD) amplifier S2 Single-supply operation: 2.0 V to 3.5 V 10k A1 Integrated reference buffer generates virtual ground SW OPAMP+ REFOUT OPAMP Rail-to-rail output OUT 6 7 8 9 10 Internal RFI filter Figure 1. 8 kV HBM ESD rating Shutdown pin 20-lead, 4 mm 4 mm LFCSP and LFCSP SS package Qualified for automotive applications APPLICATIONS Fitness and activity heart rate monitors Portable ECG Remote health monitors Gaming peripherals Biopotential signal acquisition GENERAL DESCRIPTION The AD8232 is an integrated signal conditioning block for ECG To improve common-mode rejection of the line frequencies in and other biopotential measurement applications. It is designed the system and other undesired interferences, the AD8232 to extract, amplify, and filter small biopotential signals in the includes an amplifier for driven lead applications, such as right presence of noisy conditions, such as those created by motion leg drive (RLD). or remote electrode placement. This design allows for an The AD8232 includes a fast restore function that reduces the ultralow power analog-to-digital converter (ADC) or an duration of otherwise long settling tails of the high-pass filters. embedded microcontroller to acquire the output signal easily. After an abrupt signal change that rails the amplifier (such as a The AD8232 can implement a two-pole high-pass filter for leads off condition), the AD8232 automatically adjusts to a eliminating motion artifacts and the electrode half-cell potential. higher filter cutoff. This feature allows the AD8232 to recover This filter is tightly coupled with the instrumentation architec- quickly, and therefore, to take valid measurements soon after ture of the amplifier to allow both large gain and high-pass connecting the electrodes to the subject. filtering in a single stage, thereby saving space and cost. The AD8232 is available in a 4 mm 4 mm, 20-lead LFCSP and An uncommitted operational amplifier enables the AD8232 to a LFCSP SS package. Performance for the A grade models is create a three-pole low-pass filter to remove additional noise. specified from 0C to 70C and the models are operational from The user can select the frequency cutoff of all filters to suit 40C to +85C. Performance for the W grade models is specified over the automotive temperature range of 40C to +105C. different types of applications. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20122020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 10866-001AD8232 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Standby Operation ..................................................................... 21 Applications ...................................................................................... 1 Input Protection ......................................................................... 21 Functional Block Diagram .............................................................. 1 Radio Frequency Interference (RFI) ....................................... 22 General Description ......................................................................... 1 Power Supply Regulation and Bypassing ................................ 22 Revision History ............................................................................... 2 Input Referred Offsets ............................................................... 22 Specifications .................................................................................... 4 Layout Recommendations ........................................................ 22 Absolute Maximum Ratings ........................................................... 7 Applications Information ............................................................. 23 ESD Caution.................................................................................. 7 Eliminating Electrode Offsets ................................................... 23 Pin Configuration and Function Descriptions ............................ 8 High-Pass Filtering .................................................................... 23 Typical Performance Characteristics ............................................. 9 Low-Pass Filtering and Gain .................................................... 26 Instrumentation Amplifier Performance Curves .................... 9 Driving Analog-to-Digital Converters .................................... 26 Operational Amplifier Performance Curves .......................... 12 Driven Electrode ........................................................................ 26 Right Leg Drive (RLD) Amplifier Performance Curves ....... 15 Application Circuits ....................................................................... 27 Reference Buffer Performance Curves .................................... 16 Heart Rate Measurement Next to the Heart .......................... 27 System Performance Curves ..................................................... 17 Exercise Application: Heart Rate Measured at the Hands ... 27 Theory of Operation ...................................................................... 18 Cardiac Monitor Configuration ............................................... 28 Architecture Overview .............................................................. 18 Portable Cardiac Monitor with Elimination of Motion Artifacts ....................................................................................... 28 Instrumentation Amplifier ....................................................... 18 Packaging and Ordering Information ......................................... 30 Operational Amplifier ............................................................... 18 Outline Dimensions ................................................................... 30 Right Leg Drive Amplifier ......................................................... 19 Ordering Guide .......................................................................... 31 Reference Buffer ......................................................................... 19 Fast Restore Circuit .................................................................... 19 Leads Off Detection ................................................................... 20 REVISION HISTORY 3/2020Rev. C to Rev. D 3/2017Rev. A to Rev. B Added LFCSP SS Package ........................................... Throughout Updated Outline Dimensions ...................................................... 27 Changes to Features Section and General Description Section ...... 1 Changes to Ordering Guide .......................................................... 27 Changes to Specifications Section and Table 1 ............................ 4 Changes to Operating Temperature Range Parameter, Table 2 ...... 7 2/2013Rev. 0 to Rev. A Changes to Figure 16 to Figure 20 ............................................... 11 Changes to Table 1 ............................................................................ 4 Changes to Figure 29 ..................................................................... 13 Changes to Table 2 ............................................................................ 6 Changes to Figure 32 and Figure 33 ............................................ 14 Change to Figure 17 .......................................................................... 9 Changes to Figure 35 ..................................................................... 15 Changes to Figure 22 and Figure 25 ............................................ 11 Changes to Figure 42 ..................................................................... 16 Changes to Figure 34 and Figure 36 ............................................ 14 Changes to Figure 43 and Figure 44 ............................................ 17 Changes to Figure 45, Architecture Overview Section, and Changes to Figure 45 ..................................................................... 18 Instrumentation Amplifier Section ............................................. 17 Added Figure 70 ............................................................................. 30 Changes to Right Leg Drive Amplifier Section, Reference Buffer Changes to Ordering Guide .......................................................... 31 Section, Fast Restore Circuit Section, and Figure 48 Added Figure 46, Renumbered Sequentially ........................................... 18 6/2018Rev. B to Rev. C Changes to Figure 49 ..................................................................... 19 Changes to Figure 24 ..................................................................... 10 Changes to AC Leads Off Detection Section and Standby Changes to Radio Frequency Interference (RFI) Section ......... 20 Operation Section........................................................................... 20 Updated Outline Dimensions ....................................................... 27 Changes to Input Referred Offsets Section ................................. 21 Changes to Figure 53 and High-Pass Filtering Section ............ 22 Rev. D Page 2 of 32