10 MHz, 20 V/s, G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier Data Sheet AD8250 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR A1 A0 Small package: 10-lead MSOP 2 6 5 4 Programmable gains: 1, 2, 5, 10 LOGIC Digital or pin-programmable gain setting IN 1 Wide supply: 5 V to 15 V Excellent dc performance High CMRR 98 dB (minimum), G = 10 7 OUT Low gain drift: 10 ppm/C (maximum) Low offset drift: 1.7 V/C (maximum), G = 10 Excellent ac performance 10 +IN Fast settling time: 615 ns to 0.001% (maximum) AD8250 High slew rate: 20 V/s (minimum) 8 3 9 Low distortion: 110 dB THD at 1 kHz +V V REF S S High CMRR over frequency: 80 dB to 50 kHz (minimum) Figure 1. Low noise: 18 nV/Hz, G = 10 (maximum) Low power: 4.1 mA 25 G = 10 APPLICATIONS 20 Data acquisition G = 5 15 Biomedical analysis Test and measurement 10 G = 2 5 GENERAL DESCRIPTION G = 1 0 The AD8250 is an instrumentation amplifier with digitally programmable gains that has G input impedance, low output 5 noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters 10 1k 10k 100k 1M 10M 100M (ADCs). It has a high bandwidth of 10 MHz, low THD of 110 FREQUENCY (Hz) dB and fast settling time of 615 ns (maximum) to 0.001%. Offset Figure 2. Gain vs. Frequency drift and gain drift are guaranteed to 1.7 V/C and 10 ppm/C, respectively, for G = 10. In addition to its wide input common Table 1. Instrumentation Amplifiers by Category voltage range, it boasts a high common-mode rejection of 80 dB General Mil Low High Speed at G = 1 from dc to 50 kHz. The combination of precision dc Purpose Zero Drift Grade Power PGA performance coupled with high speed capabilities makes the 1 1 1 AD8220 AD8231 AD620 AD627 AD8250 AD8250 an excellent candidate for data acquisition. Furthermore, 1 1 AD8221 AD8553 AD621 AD623 AD8251 1 1 this monolithic solution simplifies design and manufacturing AD8222 AD8555 AD524 AD8223 AD8253 1 1 and boosts performance of instrumentation by maintaining a AD8224 AD8556 AD526 1 AD8228 AD8557 AD624 tight match of internal resistors and amplifiers. 1 Rail-to-rail output. The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8250 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the 40C to +85C temperature range, making to use the transparent gain mode where the state of the logic levels it an excellent solution for applications where size and packing at the gain port determines the gain. density are important considerations. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com GAIN (dB) 06288-001 06288-023AD8250 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Bias Current Return Path ............................................... 17 Applications ....................................................................................... 1 Input Protection ......................................................................... 17 General Description ......................................................................... 1 Reference Terminal .................................................................... 18 Functional Block Diagram .............................................................. 1 Common-Mode Input Voltage Range ..................................... 18 Revision History ............................................................................... 2 Layout .......................................................................................... 18 Specifications ..................................................................................... 3 RF Interference ........................................................................... 19 Timing Diagram ........................................................................... 5 Driving an ADC ......................................................................... 19 Absolute Maximum Ratings ............................................................ 6 Applications ..................................................................................... 20 Maximum Power Dissipation ..................................................... 6 Differential Output .................................................................... 20 ESD Caution .................................................................................. 6 Setting Gains with a Microcontroller ...................................... 20 Pin Configuration and Function Descriptions ............................. 7 Data Acquisition ......................................................................... 21 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 22 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 22 Gain Selection ............................................................................. 15 Power Supply Regulation and Bypassing ................................ 17 REVISION HISTORY Changes to Table 3 ............................................................................. 6 5/13Rev. B to Rev. C Added Figure 17 Renumbered Sequentially ................................. 9 Changed 49.9 to 100 in Driving an ADC Section and Changes to Figure 23 ...................................................................... 10 Figure 55 .......................................................................................... 19 Changes to Figure 24 to Figure 26 ................................................ 11 Added Figure 29 ............................................................................. 11 11/10Rev. A to Rev. B Changes to Figure 31 ...................................................................... 12 Deleted Figure 43 to Figure 46 Renumbered Sequentially ...... 14 Changes to Voltage Offset, Offset RTI VOS, Average Inserted Figure 45 and Figure 46 .................................................. 14 Temperature Coefficient Parameter in Table 2 ............................. 3 Changes to Timing for Latched Gain Mode Section ................. 16 Updated Outline Dimensions ....................................................... 22 Changes to Layout Section and Coupling Noise Section .......... 18 5/08Rev. 0 to Rev. A Changes to Figure 59 ...................................................................... 21 Changes to Table 1 ............................................................................ 1 1/07Revision 0: Initial Version Changes to Table 2 ............................................................................ 3 Rev. C Page 2 of 24