10 MHz, 20 V/s, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier AD8251 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR A1 A0 Small package: 10-lead MSOP 2 6 5 4 Programmable gains: 1, 2, 4, 8 LOGIC IN 1 Digital or pin-programmable gain setting Wide supply: 5 V to 15 V Excellent dc performance 7 High CMRR: 98 dB (minimum), G = 8 OUT Low gain drift: 10 ppm/C (maximum) Low offset drift: 1.8 V/C (maximum), G = 8 Excellent ac performance +IN 10 Fast settling time: 785 ns to 0.001% (maximum) AD8251 High slew rate: 20 V/s (minimum) 8 3 9 Low distortion: 110 dB THD at 1 kHz, 10 V swing +V V REF S S High CMRR over frequency: 80 dB to 50 kHz (minimum) Figure 1. Low noise: 18 nV/Hz, G = 8 (maximum) 25 Low power: 4.1 mA 20 APPLICATIONS G = 8 Data acquisition 15 G = 4 Biomedical analysis Test and measurement 10 G = 2 GENERAL DESCRIPTION 5 The AD8251 is an instrumentation amplifier with digitally G = 1 0 programmable gains that has G input impedance, low output noise, and low distortion, making it suitable for interfacing with 5 sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of 110 dB, 10 1k 10k 100k 1M 10M 100M and fast settling time of 785 ns (maximum) to 0.001%. Offset FREQUENCY (Hz) drift and gain drift are guaranteed to 1.8 V/C and 10 ppm/C, Figure 2. Gain vs. Frequency respectively, for G = 8. In addition to its wide input common Table 1. Instrumentation Amplifiers by Category voltage range, it boasts a high common-mode rejection of 80 dB General Mil Low High Speed at G = 1 from dc to 50 kHz. The combination of precision dc Purpose Zero Drift Grade Power PGA performance coupled with high speed capabilities makes the 1 1 1 AD8220 AD8231 AD620 AD627 AD8250 AD8251 an excellent candidate for data acquisition. Furthermore, 1 1 AD8221 AD8553 AD621 AD623 AD8251 this monolithic solution simplifies design and manufacturing 1 1 AD8222 AD8555 AD524 AD8223 AD8253 and boosts performance of instrumentation by maintaining a 1 1 AD8224 AD8556 AD526 tight match of internal resistors and amplifiers. 1 AD8228 AD8557 AD624 The AD8251 user interface consists of a parallel port that allows 1 Rail-to-rail output. users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8251 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the 40C to +85C temperature range, making it to use the transparent gain mode where the state of the logic an excellent solution for applications where size and packing levels at the gain port determines the gain. density are important considerations. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 06287-001 06287-002AD8251 TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Regulation and Bypassing ................................ 18 Applications....................................................................................... 1 Input Bias Current Return Path ............................................... 18 General Description ......................................................................... 1 Input Protection ......................................................................... 18 Functional Block Diagram .............................................................. 1 Reference Terminal .................................................................... 19 Revision History ............................................................................... 2 Common-Mode Input Voltage Range ..................................... 19 Specifications..................................................................................... 3 Layout .......................................................................................... 19 Timing Diagram ........................................................................... 5 RF Interference ........................................................................... 20 Absolute Maximum Ratings............................................................ 6 Driving an ADC ......................................................................... 20 Maximum Power Dissipation ..................................................... 6 Applications..................................................................................... 21 ESD Caution.................................................................................. 6 Differential Output .................................................................... 21 Pin Configuration and Function Descriptions............................. 7 Setting Gains with a Microcontroller ...................................... 21 Typical Performance Characteristics ............................................. 8 Data Acquisition......................................................................... 22 Theory of Operation ...................................................................... 16 Outline Dimensions....................................................................... 23 Gain Selection ............................................................................. 16 Ordering Guide .......................................................................... 23 REVISION HISTORY 11/10Rev. A to Rev. B Changes to Table 2.............................................................................3 Changes to Voltage Offset, Offset RTI V , Average TC Changes to Table 3.............................................................................6 OS Parameter in Table 2......................................................................... 3 Inserted Figure 17 Renumbered Sequentially ..............................9 Updated Outline Dimensions ....................................................... 23 Inserted Figure 29........................................................................... 11 Changes to Timing for Latched Gain Mode Section ................. 17 5/08Rev. 0 to Rev. A Changes to Table 1............................................................................ 1 5/07Revision 0: Initial Version Rev. B Page 2 of 24