+3 Volt, Serial Input a Complete 12-Bit DAC AD8300 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 12-Bit DAC No External Components 12-BIT REF V OUT Single +3 Volt Operation DAC 12 0.5 mV/Bit with 2.0475 V Full Scale V DD CLR DAC 6 ms Output Voltage Settling Time REGISTER LD Low Power: 3.6 mW 12 GND CS EN Compact SO-8 1.5 mm Height Package CLK SERIAL REGISTER APPLICATIONS AD8300 SDI Portable Communications Digitally Controlled Calibration Servo Controls PC Peripherals GENERAL DESCRIPTION A double buffered serial data interface offers high speed, three- The AD8300 is a complete 12-bit, voltage-output digital-to- wire, DSP and microcontroller compatible inputs using data in analog converter designed to operate from a single +3 volt sup- (SDI), clock (CLK) and load strobe (LD) pins. A chip select ply. Built using a CBCMOS process, this monolithic DAC (CS) pin simplifies connection of multiple DAC packages by offers the user low cost, and ease-of-use in single-supply +3 volt enabling the clock input when active low. Additionally, a CLR systems. Operation is guaranteed over the supply voltage range input sets the output to zero scale at power on or upon user of +2.7 V to +5.5 V making this device ideal for battery oper- demand. ated applications. The AD8300 is specified over the extended industrial (40 C to The 2.0475 V full-scale voltage output is laser trimmed to +85 C) temperature range. AD8300s are available in plastic maintain accuracy over the operating temperature range of the DIP, and low profile 1.5 mm height SO-8 surface mount packages. device. The binary input data format provides an easy-to-use one-half-millivolt-per-bit software programmability. The voltage outputs are capable of sourcing 5 mA. 3.0 1.00 V = +2.7V DD 0.75 DVFS 1 LSB T = 408C, +258C, +1258C A 2.8 DATA = FFF H 0.50 T = +258C A 0.25 2.6 0.00 PROPER OPERATION 2.4 WHEN V SUPPLY DD 0.25 VOLTAGE ABOVE CURVE 0.50 2.2 = 408C = +258C 0.75 = +1258C 2.0 1.00 0.01 0.1 1.0 10 0 1024 2048 3072 4096 OUTPUT LOAD CURRENT mA DIGITAL INPUT CODE Decimal Figure 1. Minimum Supply Voltage vs. Load Figure 2. Linearity Error vs. Digital Code and Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD8300SPECIFICATIONS +3 V OPERATION ( V = +5 V 6 10%, 408C T +858C, unless otherwise noted) DD A Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 1 12 Bits Relative Accuracy INL 2 1/2 +2 LSB 2 Differential Nonlinearity DNL Monotonic 1 1/2 +1 LSB Zero-Scale Error V Data = 000 +1/2 +3 mV ZSE H 3 Full-Scale Voltage V Data = FFF 2.039 2.0475 2.056 Volts FS H Full-Scale Tempco TCV Notes 3, 4 16 ppm/ C FS ANALOG OUTPUT Output Current (Source) I Data = 800 , D V = 5 LSB 5 mA OUT H OUT Output Current (Sink) I Data = 800 , D V = 5 LSB 2 mA OUT H OUT Load Regulation L R = 200 W to , Data = 800 1.5 5 LSB REG L H Output Resistance to GND R Data = 000 30 W OUT H 4 Capacitive Load C No Oscillation 500 pF L LOGIC INPUTS 0.6 V Logic Input Low Voltage V IL Logic Input High Voltage V 2.1 V IH Input Leakage Current I 10 m A IL Input Capacitance C 10 pF IL INTERFACE TIMING 4, 5 SPECIFICATIONS Clock Width High t 40 ns CH Clock Width Low t 40 ns CL Load Pulsewidth t 50 ns LDW Data Setup t 15 ns DS Data Hold t 15 ns DH Clear Pulsewidth t 40 ns CLRW Load Setup t 15 ns LD1 Load Hold t 40 ns LD2 Select t 40 ns CSS Deselect t 40 ns CSH 4 AC CHARACTERISTICS Voltage Output Settling Time t To 0.2% of Full Scale 7 m s S 6 To 1 LSB of Final Value 14 m s Output Slew Rate SR Data = 000 to FFF to 000 2.0 V/m s H H H DAC Glitch 15 nV/s Digital Feedthrough 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range V DNL < 1 LSB 2.7 5.5 V DD RANGE Positive Supply Current I V = 3 V, V = 0 V, Data = 000 1.2 1.7 mA DD DD IL H V = 3.6 V, V = 2.3 V, Data = FFF 1.9 3.0 mA DD IH H Power Dissipation P V = 3 V, V = 0 V, Data = 000 3.6 5.1 mW DISS DD IL H Power Supply Sensitivity PSS D V = 5% 0.001 0.005 %/% DD NOTES 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. 2 REV. A