Dual-Channel Ultralow Noise Amplifier with Selectable Gain and Input Impedance Data Sheet AD8432 FEATURES FUNCTIONAL BLOCK DIAGRAM ENB VPS1 VPS2 COMM Low noise Input voltage noise: 0.85 nV/Hz BIAS Current noise: 2.0 pA/Hz AD8432 High speed INH1 OPH1 200 MHz bandwidth (G = 12.04 dB) IND1 LNA1 295 V/s slew rate OPL1 Selectable gain GMH1 GOH1 G = 12.04 dB (4) GOL1 INL1 G = 18.06 dB (8) GML1 G = 21.58 dB (12) INH2 OPH2 G = 24.08 dB (16) IND2 LNA2 OPL2 Active input impedance matching GMH2 Integrated input clamp diodes GOH2 Single-ended input, differential output INL2 GOL2 GML2 Supply range: 4.5 V to 5.5 V Low power: 60 mW/channel Figure 1. APPLICATIONS CW Doppler ultrasound front ends Low noise preamplification Predriver for I/Q demodulators and phase shifters Wideband analog-to-digital drivers GENERAL DESCRIPTION The AD8432 is a dual-channel, low power, ultralow noise The AD8432 achieves 0.85 nV/Hz input-referred voltage noise for amplifier with selectable gain and active impedance matching. a gain of 12.04 dB. The AD8432s ultralow noise, low distortion, Each channel has a single-ended input, differential output, and gain accuracy, and channel-to-channel matching are ideal for integrated input clamps. By pin strapping the gain setting pins, four high performance ultrasound systems and for processing I/Q accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB demodulator signals. (4, 8, 12, and 16, respectively) are possible. A bandwidth of The AD8432 operates on a single supply of 5 V at 24 mA. It is 200 MHz at G = 12.04 dB makes this amplifier well suited for many available in a 4 mm 4 mm, 24-lead LFSCP. The LFCSP features high speed applications. an exposed paddle that provides a low thermal resistance path to The exceptional noise performance of the AD8432 is made the PCB, which enables more efficient heat transfer and increases possible by the active impedance matching. Using a feedback reliability. The operating temperature range is 40C to +85C. network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. Impedance matching and low noise in the AD8432 allow designers to create wider dynamic range systems that are able to detect even very low level signals. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08341-001AD8432 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 18 Applications ....................................................................................... 1 Low Noise Amplifier (LNA) ..................................................... 18 Functional Block Diagram .............................................................. 1 Gain Setting Technique ............................................................. 18 General Description ......................................................................... 1 Active Input Resistance Matching ............................................ 19 Revision History ............................................................................... 2 Applications Information .............................................................. 21 Specif icat ions ..................................................................................... 3 Typical Setup ............................................................................... 21 Absolute Maximum Ratings ............................................................ 5 I/Q Demodulation Front End ................................................... 23 Thermal Resistance ...................................................................... 5 Differential-to-Single-Ended Conversion ............................... 24 Maximum Power Dissipation ..................................................... 5 Evaluation Board ............................................................................ 25 ESD Caution .................................................................................. 5 Connection and Operation ....................................................... 25 Pin Configuration and Function Descriptions ............................. 6 Schematic..................................................................................... 28 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 29 Test Circuits ..................................................................................... 16 Ordering Guide .......................................................................... 29 REVISION HISTORY 3/2017Rev. C to Rev. D 3/2011Rev. A to Rev. B Changed CP-24-7 to CP-24-15 .................................... Throughout Changes to Format ......................................................................... 21 Changes to Outline Dimensions ................................................... 29 Changes to Ordering Guide .......................................................... 29 2/2010Rev. 0 to Rev. A Changes to General Description ..................................................... 1 7/2012Rev. B to Rev. C Changes to Figure 5, Figure 6, Figure 7, Figure 8 .......................... 7 Changes to Figure 1 .......................................................................... 1 Added Figure 27, Figure 29, and Figure 31, Renumbered Changes to Figure 65 ...................................................................... 18 Sequentially ..................................................................................... 11 Change to Figure 69 ....................................................................... 21 Added Figure 33 and Figure 35 .................................................... 12 Changes to Table 7 .......................................................................... 22 Changes to Figure 58 ...................................................................... 16 Deleted Gain Settings Section and Table 8 .................................. 25 Changes to Evaluation Board Section and Figure 73 Added 10/2009Revision 0: Initial Version Connection and Operation Section and Table 8 ........................ 25 Added Figure 74 to Figure 78, Renumbered Sequentially ........ 26 Added Figure 79 .............................................................................. 27 Changes to Figure 80 ...................................................................... 28 Updated Outline Dimensions ....................................................... 29 Rev. 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