Precision Analog Front End and Controller for Battery Test/Formation Systems Data Sheet AD8450 FEATURES GENERAL DESCRIPTION Integrated constant current and voltage modes with The AD8450 is a precision analog front end and controller for automatic switchover testing and monitoring battery cells. A precision programmable Charge and discharge modes gain instrumentation amplifier (PGIA) measures the battery Precision voltage and current measurement charge/discharge current, and a programmable gain difference Integrated precision control feedback blocks amplifier (PGDA) measures the battery voltage (see Figure 1). Precision interface to PWM or linear power converters Internal laser trimmed resistor networks set the gains for the Programmable gain settings PGIA and the PGDA, optimizing the performance of the Current sense gains: 26, 66, 133, and 200 AD8450 over the rated temperature range. PGIA gains are 26, Voltage sense gains: 0.2, 0.27, 0.4, and 0.8 66, 133, and 200. PGDA gains are 0.2, 0.27, 0.4, and 0.8. Programmable OVP and OCP fault detection Voltages at the ISET and VSET inputs set the desired constant Current sharing and balancing current (CC) and constant voltage (CV) values. CC to CV Excellent ac and dc performance switching is automatic and transparent to the system. Maximum offset voltage drift: 0.6 V/C A TTL logic level input, MODE, selects the charge or discharge Maximum gain drift: 3 ppm/C mode (high for charge, low for discharge). An analog output, Low current sense amplifier input voltage noise: 9 nV/Hz VCTRL, interfaces directly with the Analog Devices, Inc., Current sense CMRR: 126 dB minimum (gain = 200) ADP1972 PWM controller. TTL compliant logic The AD8450 includes resistor programmable overvoltage and APPLICATIONS overcurrent detection and current sharing circuitry. Current Battery cell formation and testing sharing is used to balance the output current of multiple Battery module testing bridged channels. The AD8450 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with functionality, and overall reliability in a space-saving package. The AD8450 is available in an 80-lead, 14 mm 14 mm 1 mm LQFP package and is rated for an operating temperature of 40C to +85C. FUNCTIONAL BLOCK DIAGRAM ISREFH/ IVE0/ ISREFL ISMEA ISET IVE1 VINT AD8450 CSH ISVP CONSTANT CURRENT GAIN CURRENT LOOP SHARING IMAX 26, 66, NETWORK FILTER 133, 200 AND MUX VCLP ISVN CURRENT SENSE PGIA 1 VCTRL (CHARGE/ DISCHARGE) MODE SWITCHING VCLN VOLTAGE SENSE PGDA VOLTAGE BVPx VREF REFERENCE GAIN 0.2, 0.27, CONSTANT NETWORK 0.4, 0.8 VOLTAGE LOOP FILTER FAULT BVNx FAULT DETECTION BVREFH/ BVMEA VSET VVE0/ VVP0 VSETBF VINT OVPS/ OCPS/ BVREFL VVE1 OVPR OCPR Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 11966-001AD8450 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overcurrent and Overvoltage Comparators ........................... 27 Applications ....................................................................................... 1 Current Sharing Bus and IMAX Output ................................. 28 General Description ......................................................................... 1 Applications Information .............................................................. 29 Functional Block Diagram .............................................................. 1 Functional Description .............................................................. 29 Revision History ............................................................................... 2 Power Supply Connections ....................................................... 29 Specifications ..................................................................................... 3 Power Supply Sequencing ......................................................... 29 Absolute Maximum Ratings ............................................................ 8 Power-On Sequence ................................................................... 29 Thermal Resistance ...................................................................... 8 Power-Off Sequence ................................................................... 30 ESD Caution .................................................................................. 8 PGIA Connections ..................................................................... 30 Pin Configuration and Function Descriptions ............................. 9 PGDA Connections ................................................................... 31 Typical Performance Characteristics ........................................... 11 Battery Current and Voltage Control Inputs (ISET and VSET) ....................................................................................................... 31 PGIA Characteristics ................................................................. 11 Loop Filter Amplifiers ............................................................... 32 PGDA Characteristics ................................................................ 13 Connecting to a PWM Controller (VCTRL Pin) ...................... 32 CC and CV Loop Filter Amplifiers, Uncommitted Op Amp, and VSET Buffer ......................................................................... 15 Overvoltage and Overcurrent Comparators ........................... 32 VINT Buffer ................................................................................ 17 Step by Step Design Example .................................................... 32 Current Sharing Amplifier ........................................................ 18 Additional Information ............................................................. 33 Comparators ................................................................................ 19 Evaluation Board ............................................................................ 34 Reference Characteristics .......................................................... 20 Introduction ................................................................................ 34 Theory of Operation ...................................................................... 21 Features and Tests ....................................................................... 34 Introduction ................................................................................ 21 Testing the AD8450-EVALZ ..................................................... 34 Programmable Gain Instrumentation Amplifier (PGIA) ..... 23 Using the AD8450 ...................................................................... 36 Programmable Gain Difference Amplifier (PGDA) .............. 24 Schematic and Artwork ............................................................. 37 CC and CV Loop Filter Amplifiers .......................................... 24 Outline Dimensions ....................................................................... 41 Compensation ............................................................................. 26 Ordering Guide .......................................................................... 41 VINT Buffer ................................................................................ 26 MODE Pin, Charge and Discharge Control ........................... 26 7/14Rev. 0 to Rev. A REVISION HISTORY Changes to General Description ..................................................... 1 8/15Rev. A to Rev. B Changes to Pin 39 and Pin 80 Descriptions ................................ 10 Changes to Table 2 ............................................................................ 8 Changes to Introduction Section and Figure 50 ........................ 22 Changes to Figure 52 ...................................................................... 24 Added Power Supply Sequencing Section and Power-On Changes to Figure 55 ...................................................................... 26 Sequence Section ............................................................................ 29 Changes to Current Sharing Bus and IMAX Output Section .. 27 Added Power-Off Sequence .......................................................... 30 Changes to Figure 58 ...................................................................... 28 Added Additional Information Section ....................................... 33 Changes to Figure 59 ...................................................................... 30 Changes to Step 4: Determine the Control Voltage for the CC Changes to Evaluation Board Section.......................................... 33 Loop, the Shunt Resistor, and the PGIA Gain Section .............. 33 1/14Revision 0: Initial Version Rev. B Page 2 of 41