+5 Volt, Parallel Input a Complete Dual 12-Bit DAC AD8582 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete Dual 12-Bit DAC No External Components AD8582 V DD 12 Single +5 Volt Operation 12-BIT DAC A LDA V OUTA DAC A 1 mV/Bit with 4.095 V Full Scale REGISTER True Voltage Output, 5 mA Drive INPUT A CS Very Low Power: 5 mW REGISTER A/B APPLICATIONS 12 2 DATA REFERENCE V REF Digitally Controlled Calibration Portable Equipment INPUT B REGISTER Servo Controls Process Control Equipment 12 DAC B 12-BIT LDB PC Peripherals REGISTER V OUTB DAC B AGND MSB DGND RST GENERAL DESCRIPTION The high speed parallel data interface connects to the fastest The AD8582 is a complete, parallel input, dual 12-bit, voltage processors without wait states. The double-buffered input struc- output DAC designed to operate from a single +5 volt supply. ture allows the user to load the input registers one at a time, Built using a CBCMOS process, this monolithic DAC offers the then a single load strobe tied to both LDA + LDB inputs will user low cost, and ease-of-use in +5 volt only systems. update both DAC outputs simultaneously. LDA and LDB can also be activated independently to immediately update their re- Included on the chip, in addition to the DACs, are a rail-to-rail spective DAC registers. An address input decodes DAC A or amplifier, latch and reference. The reference (V ) is trimmed REF DAC B when the chip select CS input is strobed. An asynchro- to 2.5 volts output, and the on-chip amplifier gains up the DAC nous reset input sets the output to zero scale. The MSB bit can output to 4.095 volts full scale. The user needs only supply a +5 be used to establish a preset to midscale when the reset input is volt supply. strobed. The AD8582 is coded natural binary. The op amp output The AD8582 is available in the 24-pin plastic DIP and the sur- swings from 0 volt to +4.095 volts for a one-millivolt-per-bit face mount SOIC-24. Each part is fully specified for operation resolution, and is capable of driving 5 mA. Operation down to over 40C to +85C, and the full +5 V 5% power supply 4.3 V is possible with output load currents less than 1 mA. range. 5.0 2.0 VFS 1 LSB DATA = FFF H 1.5 V = +5V T = +25C DD 4.8 A T = 55C, +25C, +85C A 1.0 4.6 0.5 PROPER OPERATION WHEN V SUPPLY 0.0 DD 4.4 VOLTAGE ABOVE 0.5 CURVE 4.2 1.0 = +25C & +85C = 55C 1.5 4.0 2.0 0.01 0.1 1.0 10 100 0 1024 2048 3072 4096 OUTPUT LOAD CURRENT mA DIGITAL INPUT CODE Decimal Figure 1. Minimum Supply Voltage vs. Load Figure 2. Linearity Error vs. Digital Code and Temperature REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 V MIN Volts DD LINEARITY ERROR LSBAD8582SPECIFICATIONS ( V = +5.0 V 5%, R = No Load, 40C T +85C, unless otherwise noted) DD L A ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 1 12 Bits Relative Accuracy INL 2 3/4 +2 LSB Differential Nonlinearity DNL Monotonic 1 3/4 +1 LSB Zero-Scale Error V Data = 000 +0.2 +3 mV ZSE H 2 Full-Scale Voltage V Data = FFF , 4.079 4.095 4.111 V FS H Full-Scale Tempco TCV Notes 2 and 3 16 ppm/C FS MATCHING PERFORMANCE Linearity Matching Error V A/B 1 LSB FS REFERENCE OUTPUT Output Voltage V 2.484 2.500 2.516 V REF Output Source Current I Note 4 5 mA REF Line Rejection LN 0.08 %/V REJ Load Regulation LD I = 0 mA to 5 mA 0.1 %/mA REG REF ANALOG OUTPUT Output Current I Data = 800 5mA OUT H Load Regulation at Half Scale LD R = 402 to , Data = 800 1 3 LSB REG L H 3 Capacitive Load C No Oscillation 500 pF L 3 DYNAMIC CHARACTERISTICS Crosstalk C >64 dB T 5 Voltage Output Settling Time t To 1 LSB of Final Value 16 s S Digital Feedthrough F Signal Measured at DAC Output, While 35 nV s T Changing Data (LDA = LDB = 1) LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 A IL Input Capacitance C Note 3 10 pF IL 3, 6 TIMING SPECIFICATIONS Chip Select Pulse Width t 30 ns CSW DAC Select Setup t 30 ns AS DAC Select Hold t 0ns AH Data Setup t 30 ns DS Data Hold t 10 ns DH Load Setup t 20 ns LS Load Hold t 10 ns LH Load Pulse Width t 20 ns LDW Reset Pulse Width t 30 ns RSW SUPPLY CHARACTERISTICS Positive Supply Current I V = 2.4 V, V = 0.8 V 4 7 mA DD IH IL V = 0 V, V = +5 V 1 2 mA IL DD 7 Power Dissipation P V = 2.4 V, V = 0.8 V 20 35 mW DISS IH IL V = 0 V, V = +5 V 5 10 mW IL DD Power Supply Sensitivity PSS V = 5% 0.002 0.004 %/% DD NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V pin. Use external buffer if setting up a virtual ground. REF 5 Settling time is not guaranteed for the first six codes 0 through 5. 6 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. R F 7 Power dissipation is a calculated value I 5 V. DD Specifications subject to change without notice. REV. 0 2