12 Channel, 8-Bit TrimDACs a with Power Shutdown AD8802/AD8804 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Cost Replaces 12 Potentiometers V CS AD8802/AD8804 DD Individually Programmable Outputs V REFH CLK 3-Wire SPI Compatible Serial Input DAC D7 O1 1 O2 Power Shutdown <55 mWatts Including I & I DD REF DAC EN O3 D11 REG Midscale Preset, AD8802 O4 1 D10 ADDR D0 Separate V Range Setting, AD8804 O5 D9 DEC REFL R D8 O6 +3 V to +5 V Single Supply Operation D7 O7 O8 SER APPLICATIONS O9 REG Automatic Adjustment O10 SDI DD0 O11 Trimmer Replacement D7 DAC O12 12 Video and Audio Equipment Gain and Offset Adjustment DAC 8 Portable and Battery Operated Equipment REG 12 D0 R SHDN GENERAL DESCRIPTION GND V RS REFL The 12-channel AD8802/AD8804 provides independent digitally- (AD8802 ONLY) (AD8804 ONLY) controllable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC allows replacement of the mechanical trimmer function in new designs. The AD8802/ Each DAC has its own DAC latch that holds its output state. AD8804 is ideal for dc voltage adjustment applications. These DAC latches are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire Easily programmed by serial interfaced microcontroller ports, serial input digital interface. The serial-data-input word is the AD8802 with its midscale preset is ideal for potentiometer decoded where the first 4 bits determine the address of the DAC replacement where adjustments start at a nominal value. Appli- latches to be loaded with the last 8 bits of data. The AD8802/ cations such as gain control of video amplifiers, voltage con- AD8804 consumes only 10 A from 5 V power supplies. In ad- trolled frequencies and bandwidths in video equipment, dition, in shutdown mode reference input current consumption geometric correction and automatic adjustment in CRT com- is also reduced to 10 A while saving the DAC latch settings for puter graphic displays are a few of the many applications ideally use after return to normal operation. suited for these parts. The AD8804 provides independent con- trol of both the top and bottom end of the potentiometer divider The AD8802/AD8804 is available in the 20-pin plastic DIP, the allowing a separate zero-scale voltage setting determined by the SOIC-20 surface mount package, and the 1 mm thin TSSOP-20 V pin. This is helpful for maximizing the resolution of REFL package. devices with a limited allowable voltage control range. Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common reference- voltage input. TrimDAC is a registered trademark of Analog Devices, Inc. REV. 0 Analog Devices, Inc., 1995 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 otherwise under any patent or patent rights of Analog Devices.(V = +3 V 6 10% or +5 V 6 10%, V = +V , V = 0 V, 408C DD REFH DD REFL AD8802/AD8804SPECIFICATIONS T +858C unless otherwise noted) A 1 Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY Specifications apply to all DACs Resolution N 8 Bits Differential Nonlinearity Error DNL Guaranteed Monotonic 1 1/4 +1 LSB Integral Nonlinearity Error INL 1.5 1/2 +1.5 LSB Full-Scale Error G 1 1/2 +1 LSB FSE Zero Code Error V 1 1/4 +1 LSB ZSE DAC Output Resistance R 35 8 k OUT Output Resistance Match R/R 1.5 % O REFERENCE INPUT 2 Voltage Range V 0V V REFH DD V Pin Available on AD8804 Only 0 V V REFL DD REFH Input Resistance R Digital Inputs = 55 , V = V 1.2 k REFH H REFH DD 3 REFL Input Resistance R Digital Inputs = 55 , V = V 1.2 k REFL H REFL DD 3 Reference Input Capacitance C Digital Inputs all Zeros 32 pF REF0 C Digital Inputs all Ones 32 pF REF1 DIGITAL INPUTS Logic High V V = +5 V 2.4 V IH DD Logic Low V V = +5 V 0.8 V IL DD Logic High V V = +3 V 2.1 V IH DD Logic Low V V = +3 V 0.6 V IL DD Input Current I V = 0 V or + 5 V 1 A IL IN 3 Input Capacitance C 5pF IL 4 POWER SUPPLIES Power Supply Range V Range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 10 A DD IH DD IL Supply Current (TTL) I V = 2.4 V or V = 0.8 V, V = +5.5 V 1 4 mA DD IH IL DD Shutdown Current I SHDN = 0 0.2 10 A REFH Power Dissipation P V = V or V = 0 V, V = +5.5 V 55 W DISS IH DD IL DD Power Supply Sensitivity PSRR V = +5 V 10% 0.001 0.002 %/% DD 3 DYNAMIC PERFORMANCE V Settling Time t 1/2 LSB Error Band 0.6 s OUT S 5 Crosstalk CT Between Adjacent Outputs 50 dB 3, 6 SWITCHING CHARACTERISTICS Input Clock Pulse Width t , t Clock Level High or Low 15 ns CH CL Data Setup Time t 5ns DS Data Hold Time t 5ns DH CS Setup Time t 10 ns CSS CS High Pulse Width t 10 ns CSW Reset Pulse Width t 90 ns RS CLK Rise to CS Rise Hold Time t 20 ns CSH CS Rise to Clock Rise Setup t 10 ns CS1 NOTES 1 Typicals represent average readings at +25C. 2 V can be any value between GND and V , for the AD8804 V can be any value between GND and V . REFH DD REFL DD 3 Guaranteed by design and not subject to production test. 4 Digital Input voltages V = 0 V or V for CMOS condition. DAC outputs unloaded. P is calculated from (I V ). IN DD DISS DD DD 5 Measured at a V pin where an adjacent V pin is making a full-scale voltage change (f = 100 kHz). OUT OUT 6 See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of V ) and timed from a voltage level of R F DD 1.6 V. Specifications subject to change without notice. 2 REV. 0