Octal 8-Bit TrimDAC a with Power Shutdown AD8801/AD8803 FEATURES FUNCTIONAL BLOCK DIAGRAM Low Cost (DACs 27 Omitted for Clarity) Replaces Eight Potentiometers V V REFH REFL Eight Individually Programmable Outputs Three-Wire Serial Input AD8801/AD8803 V Power Shutdown 25 mW Including I and I REFH DD REF 8 8-BIT V VDD DAC 1 OUT O1 LATCH Midscale Preset, AD8801 V REFL Separate V Range Setting, AD8803 REFL CK RS GND 8 +3 V to +5 V Single Supply Operation 1 DAC SELECT . APPLICATIONS 8 . ADDRESS Automatic Adjustment 3 Trimmer Potentiometer Replacement . Video and Audio Equipment Gain and Offset Adjustment 11-BIT . SERIAL 8 Portable and Battery Operated Equipment LATCH . SDI D . RS CK CLK V 8-BIT REFH 88 CS V LATCH DAC 8 OUT O8 GENERAL DESCRIPTION V REFL CK RS The AD8801/AD8803 provides eight digitally controlled dc 8 voltage outputs. This potentiometer divider TrimDAC allows replacement of the mechanical trimmer function in new designs. RS SHDN The AD8801/AD8803 is ideal for dc voltage adjustment applications. Easily programmed by serial interfaced microcontroller ports, the AD8801 with its midscale preset is ideal for potentiometer Internally the AD8801/AD8803 contain eight voltage output replacement where adjustments start at a nominal value. Appli- digital-to-analog converters, sharing a common reference volt- cations such as gain control of video amplifiers, voltage con- age input. trolled frequencies and bandwidths in video equipment, Each DAC has its own DAC register that holds its output state. geometric correction and automatic adjustment in CRT com- These DAC registers are updated from an internal serial-to-par- puter graphic displays are a few of the many applications ideally allel shift register that is loaded from a standard three-wire serial suited for these parts. The AD8803 provides independent con- input digital interface. Eleven data bits make up the data word trol of both the top and bottom end of the potentiometer divider clocked into the serial input register. This data word is decoded allowing a separate zero-scale voltage setting determined by the where the first 3 bits determine the address of the DAC register V pin. This is helpful for maximizing the resolution of de- REFL to be loaded with the last 8 bits of data. The AD8801/AD8803 vices with a limited allowable voltage control range. consumes only 5 A from 5 V power supplies. In addition, in shutdown mode reference input current consumption is also re- duced to 5 A while saving the DAC latch settings for use after return to normal operation. The AD8801/AD8803 is available in 16-pin plastic DIP and the 1.5 mm height SO-16 surface mount packages. See the AD8802/AD8804 for a twelve channel version of this product. TrimDAC is a registered trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(V = +3 V 6 10% or +5 V 6 10%, V = +V , V = 0 V, 408C DD REFH DD REFL T +858C unless otherwise noted) A AD8801/AD8803SPECIFICATIONS 1 Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY Specifications Apply to All DACs Resolution N 8 Bits Integral Nonlinearity Error INL 1.5 1/2 +1.5 LSB Differential Nonlinearity DNL Guaranteed Monotonic 1 1/4 +1 LSB Full-Scale Error G 4 2.8 +0.5 LSB FSE Zero-Code Error V 0.5 0.1 +0.5 LSB ZSE DAC Output Resistance R 35 8 k OUT Output Resistance Match R/R 1% O REFERENCE INPUT 2 Voltage Range V 0V V REFH DD V Pin Available on AD8803 Only 0 V V REFL DD Input Resistance R Digital Inputs = 55 , V = V 2k REFH H REFH DD 3 Reference Input Capacitance C Digital Inputs All Zeros 25 pF REF0 C Digital Inputs All Ones 25 pF REF1 DIGITAL INPUTS Logic High V V = +5 V 2.4 V IH DD Logic Low V V = +5 V 0.8 V IL DD Logic High V V = +3 V 2.1 V IH DD Logic Low V V = +3 V 0.6 V IL DD Input Current I V = 0 V or +5 V 1 A IL IN 3 Input Capacitance C 5pF IL 4 POWER SUPPLIES Power Supply Range V Range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 A DD IH DD IL Supply Current (TTL) I V = 2.4 V or V = 0.8 V, V = +5.5 V 1 4 mA DD IH IL DD Shutdown Current I SHDN = 0 0.01 5 A REFH Power Dissipation P V = V or V = 0 V, V = +5.5 V 27.5 W DISS IH DD IL DD Power Supply Sensitivity PSRR V = 5 V 10%, V = +4.5 V 0.001 0.002 %/% DD REFH Power Supply Sensitivity PSRR V = 3 V 10%, V = +2.7 V 0.01 %/% DD REFH 3 DYNAMIC PERFORMANCE V Settling Time (Positive or Negative) t 1/2 LSB Error Band 0.6 s OUT S Crosstalk CT See Note 5, f = 100 kHz 50 dB 3, 6 SWITCHING CHARACTERISTICS Input Clock Pulse Width t , t Clock Level High or Low 15 ns CH CL Data Setup Time t 5ns DS Data Hold Time t 5ns DH CS Setup Time t 10 ns CSS CS High Pulse Width t 10 ns CSW Reset Pulse Width t 60 ns RS CLK Rise to CS Rise Hold Time t 15 ns CSH CS Rise to Next Rising Clock t 10 ns CS1 NOTES 1 Typical values represent average readings measured at +25C. 2 V can be any value between GND and V , for the AD8803 V can be any value between GND and V . REFH DD REFL DD 3 Guaranteed by design and not subject to production test. 4 Digital Input voltages V = 0 V or V for CMOS condition. DAC outputs unloaded. P is calculated from (I V ). IN DD DISS DD DD 5 Measured at a V pin where an adjacent V pin is making a full-scale voltage change. OUT OUT 6 See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of V ) and timed from a voltage R F DD level of 1.6 V. Specifications subject to change without notice. 2 REV. A