8-Bit Octal, 4-Quadrant a Multiplying, CMOS TrimDAC AD8842 FEATURES FUNCTIONAL BLOCK DIAGRAM Low Cost Replaces 8 Potentiometers V A IN DECODED 50 kHz 4-Quadrant Multiplying Bandwidth ADDRESS Low Zero Output Error G V DD 8 X 8 8 8 DAC A Eight Individual Channels DAC VOUTA R 3-Wire Serial Input LOGIC LD E AD8842 500 kHz Update Data Loading Rate DATA G I 4 8 3 V Output Swing S V H IN T Midscale Preset, Zero Volts Out G E SERIAL SDI 8 R DAC H REGISTER S APPLICATIONS V H OUT CLK Automatic Adjustment Trimmer Replacement GND V SDO PR SS Vertical Deflection Amplitude Adjustment Waveform Generation and Modulation GENERAL DESCRIPTION The AD8842 consumes only 95 mW from 5 V power supplies. The AD8842 provides eight general purpose digitally controlled For single 5 V supply applications consult the DAC-8841. The voltage adjustment devices. The TrimDAC capability allows AD8842 is pin compatible with the 1 MHz multiplying band- replacement of the mechanical trimmer function in new designs. width DAC8840. The AD8842 is available in 24-pin plastic The AD8842 is ideal for ac or dc gain control of up to 50 kHz DIP and surface mount SOL-24 packages. bandwidth signals. The four-quadrant multiplying capability is useful for signal inversion and modulation often found in video RR vertical deflection circuitry. V IN Internally the AD8842 contains eight voltage output digital-to- analog converters, each with separate voltage inputs. A new V OUT current conveyor amplifier design performs the four-quadrant multiplying function with a single amplifier at the output of the current steering digital-to-analog converter. This approach of- V = V (D/128 1) fers an improved constant input resistance performance versus OUT IN previous voltage switched DACs used in TrimDAC circuits, eliminating the need for additional input buffer amplifiers. Figure 1. Functional Circuit of One 4-Quadrant Each DAC has its own DAC register that holds its output state. Multiplying Channel These DAC registers are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial CURRENT CONVEYOR AMPLIFIER input digital interface. Twelve data bits make up the data word V IN REF V OUT clocked into the serial input register. This data word is decoded V D IN I1 = V (D/1281) IN 256 R where the first 4 bits determine the address of the DAC register I2 V R (1- D) IN to be loaded with the last 8 bits of data. A serial data output pin 256 R at the opposite end of the serial register allows simple daisy R chaining in multiple DAC applications without additional exter- nal decoding logic. TrimDAC is a registered trademark of Analog Devices, Inc. Figure 2. Actual Current Conveyor Implementation of The current conveyor amplifier is a patented circuit belonging to Analog Multiplying DAC Channel Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: Fax: 781/329-4700 781/461-3113AD8842SPECIFICATIONS (V = +5 V, V = 5 V, All V x = +3 V, T = 40C to +85C, unless otherwise noted.) ELECTRICAL CHARACTERISTICS DD SS IN A Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACYAll Specifications Apply for DACs A, B, C, D, E, F, G, H Resolution N 8 Bits Integral Nonlinearity Error INL 0.2 1 LSB Differential Nonlinearity DNL All Devices Monotonic 0.4 1 LSB Full-Scale Gain Error G 2 LSB FSE PR = 0, Sets D = 80 525 mV Output Offset V BZE H Output Offset Drift TCV PR = 0, Sets D = 80 5 V/C BZ H VOLTAGE INPUTSApplies to All Inputs V x IN 1 Input Voltage Range IVR 3 4V 12 19 k Input Resistance R IN Input Capacitance C 9pF IN DAC OUTPUTSApplies to All Outputs V x OUT 1 OVR R = 10 k34V Voltage Range L Output Current I V < 1.5 LSB 3mA OUT OUT Capacitive Load C No Oscillation 500 pF L DYNAMIC PERFORMANCEApplies to All DACs 1 Full Power Gain Bandwidth GBW V x = 3 V , R = 2 k, C = 10 pF 10 50 kHz IN P L L Slew Rate Measured 10% to 90% Positive SR+ V x = +5.5 V 0.5 1.0 V/s OUT x = 5.5 V 1.0 1.8 V/s Negative SR V OUT Total Harmonic Distortion THD V x = 4 V p-p, D = FF , f = 1 kHz, 0.01 % IN H = 80 kHz, R = 1 k f LPF L Spot Noise Voltage e f = 1kHz, V = 0 V 78 nV/Hz N IN 1 LSB Error Band, D = 00 to FF 2.9 s Output Settling Time t S H H D = FF to 00 5.4 s H H Measured Between Adjacent Channel-to-Channel Crosstalk C T Channels, f = 100 kHz 72 dB Digital Feedthrough Q V x = 0 V, D = 0 to 255 5 nV-s IN 10 POWER SUPPLIES Positive Supply Current I PR = 0 V 10 14 mA DD Negative Supply Current I PR = 0 V 9 13 mA SS 2 P 95 135 mW Power Dissipation DISS Power Supply Rejection PSRR PR = 0 V, V = 5% 0.0001 0.01 %/% DD Power Supply Range PSR V , V 4.75 5.00 5.25 V DD SS DIGITAL INPUTS Logic High V 2.4 V IH 0.8 V Logic Low V IL Input Current I 10 A L 7pF Input Capacitance C IL Input Coding Offset Binary DIGITAL OUTPUT Logic High V I = 0.4 mA 3.5 V OH OH Logic Low V I = 1.6 mA 0.4 V OL OL 1 TIMING SPECIFICATIONS Input Clock Pulse Width t , t 60 ns CH CL 40 ns Data Setup Time t DS Data Hold Time t 20 ns DH 80 ns CLK to SDO Propagation Delay t PD DAC Register Load Pulse Width t 70 ns LD 50 ns Preset Pulse Width t PR Clock Edge to Load Time t 30 ns CKLD Load Edge to Next Clock Edge t 60 ns LDCK NOTES 1 Guaranteed by design, not subject to production test. 2 Calculated limit = 5 V (I + I ). DD SS Specifications subject to change without notice. 2 REV. A