MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Data Sheet AD9082 Auxiliary features FEATURES Fast frequency hopping Flexible reconfigurable common platform design Direct digital synthesis (DDS) 4 DACs and 2 ADCs (4D2A) and 2D2A options Low latency loopback modes (receive datapath data can Supports single, dual, and quad band be routed to the transmit datapaths) Datapaths and DSP blocks are fully bypassable ADC clock driver with selectable divide ratios DAC to ADC sample rate ratios of 1, 2, 3, and 4 Power amplifier downstream protection circuitry On-chip PLL with multichip synchronization On-chip temperature monitoring unit External RFCLK input option for off-chip PLL Flexible GPIO pins Maximum DAC sample rate up to 12 GSPS TDD power savings option Maximum data rate up to 12 GSPS using JESD204C SERDES JESD204B/C interface, 16 lanes up to 24.75 Gbps Useable analog bandwidth to 8 GHz 8 lanes JESD204B/C transmitter (JTx) and 8 lanes Maximum ADC sample rate up to 6 GSPS JESD204B/C receiver (JRx) Maximum data rate up to 6 GSPS using JESD204C JESD204B compliance with the maximum 15.5 Gbps Useable analog bandwidth to 8 GHz JESD204C compliance with the maximum 24.75 Gbps ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Supports real or complex digital data (8-, 12-, 16-, or 24-bit) Full-scale input voltage: 1.475 V p-p 15 mm 15 mm, 324-ball BGA with 0.8 mm pitch Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB APPLICATIONS HD2: 72 dBFS Wireless communications infrastructure HD3: 68 dBFS Microwave point to point, E-band, and 5G mmWave Worst other (excluding HD2 and HD3): 78 dBFS Broadband communications systems DAC ac performance at 12 GSPS, output at 2.6 GHz DOCSIS 3.1 and 4.0 CMTS Full-scale output current range: 6.43 mA to 37.75 mA Phased array radar and electronic warfare Two-tone IMD3 (6 dBFS per tone): 72 dBc Electronic test and measurement systems NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc GENERAL DESCRIPTION Versatile digital features The AD9082 mixed signal front-end (MxFE) is a highly integrated Selectable interpolation and decimation filters device with four 16-bit, 12 GSPS maximum sample rate, RF digital- Configurable DDC and DUC to-analog converter (DAC) cores, and two 12-bit, 6 GSPS 8 fine complex DUCs and 4 coarse complex DUCs maximum sample rate, RF analog-to-digital converter (ADC) 8 fine complex DDCs and 4 coarse complex DDCs cores. The AD9082 is well suited for applications requiring both 48-bit NCO per DUC or DDC wideband ADCs and DACs to process signal(s) that have wide Option to bypass fine and coarse DUC/DDC instantaneous bandwidth. The device features eight transmit lanes Programmable 192-tap PFIR filter for receive equalization and eight receive lanes that support 24.75 Gbps/lane JESD204C or Supports 4 different profile settings loaded via GPIO 15.5 Gbps/lane JESD204B standards. The device also has an on- Programable delay per data path chip clock multiplier and digital signal processing (DSP) capability Receive AGC support targeted at either wideband or multiband, direct to RF applications. Fast detect with low latency for fast AGC control The DSP datapaths can be bypassed to allow a direct connection Signal monitor for slow AGC control between the converter cores and the JESD204B/C data transceiver Dedicated AGC support pins port. The device also features low latency loopback, frequency Transmit DPD support hopping modes, and datapath multiplexer (mux) configurations Fine DUC channel gain control and delay adjust useful for phase array radar system and electronic warfare Coarse DDC delay adjust for DPD observation path applications. Two models for the AD9082 are offered. The 4D2AC model supports four DACs and two ADCs. The 2D2AC model supports two DACs and two ADCs. See the Ordering Guide for more information. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2021 Analog Devices, Inc. All rights reserved. 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AD9082 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B and JESD204C Interface Electrical and Speed Specifications .............................................................................. 10 Applications ...................................................................................... 1 CMOS Pin Specifications .......................................................... 11 General Description ......................................................................... 1 DAC AC Specifications ............................................................. 11 Revision History ............................................................................... 2 ADC AC Specifications ............................................................. 14 Functional Block Diagram .............................................................. 3 Timing Specifications ................................................................ 16 Specifications .................................................................................... 4 Absolute Maximum Ratings ......................................................... 17 Recommended Operating Conditions ...................................... 4 Thermal Resistance .................................................................... 17 Power Consumption .................................................................... 4 ESD Caution ............................................................................... 17 DAC DC Specifications ............................................................... 5 Pin Configuration and Function Descriptions .......................... 18 ADC DC Specifications ............................................................... 5 Typical Performance Characteristics .......................................... 23 Clock Inputs and Outputs ........................................................... 6 DAC ............................................................................................. 23 Clock Input and Phase-Locked Loop (PLL) Frequency Specifications ................................................................................ 6 ADC ............................................................................................. 28 DAC Sample Rate Specifications ............................................... 7 Theory of Operation ...................................................................... 35 ADC Sample Rate Specifications ............................................... 7 Outline Dimensions ....................................................................... 36 Input and Output Data Rate Specifications .............................. 8 Ordering Guide .......................................................................... 36 NCO Frequency Specifications .................................................. 9 REVISION HISTORY 6/2021Rev. B to Rev. C Added NCO Frequency Specifications Section and Table 10 ..... 9 Changes to Table 20 ....................................................................... 17 Added Table 11 and Table 12 .......................................................... 9 Added Table 13 and Table 14 ....................................................... 10 3/2021Rev. A to Rev. B Changes to Table 19 and Table 20 ............................................... 17 Changes to Features Section and General Description Section . 1 Changes to Table 21 ....................................................................... 19 Changes to Figure 1 .......................................................................... 3 Changes to Pin Configuration and Function Descriptions Changes to Specifications Section .................................................. 4 Section and Figure 5 ....................................................................... 18 Deleted DC Specifications Section and Table 2 Renumbered Changes to Typical Performance Characteristics Section ........ 23 Sequentially ....................................................................................... 4 Changes to Theory of Operation Section ................................... 35 Added DAC DC Specifications Section, Table 3, ADC DC Changes to Ordering Guide .......................................................... 36 Specifications Section, and Table 4 Renumbered Sequentially 5 Deleted DAC and ADC Sampling Specifications Section .......... 5 9/2020Rev. 0 to Rev. A Added Clock Inputs and Outputs Section and Table 5 .............. 6 Changes to Figure 1 .......................................................................... 3 Added DAC Sample Rate Specifications Section, Table 7, ADC Changes to Figure 5 ....................................................................... 16 Sample Rate Specifications Section, and Table 8 ......................... 7 Changes to Table 14 ....................................................................... 17 Deleted Table 6 ................................................................................. 7 Added Table 9 ................................................................................... 8 6/2020Revision 0: Initial Version Deleted Table 7 ................................................................................. 8 Rev. C Page 2 of 36