8-Bit, 1 GSPS, JESD204B, Quad ADC Data Sheet AD9094 FEATURES GENERAL DESCRIPTION JESD204B (Subclass 1 and Subclass 0) coded serial The AD9094 is an 8-bit, 1 GSPS, quad analog-to-digital converter digital outputs (ADC). The device has an on-chip buffer and a sample-and-hold Lane rates up to 15 Gbps circuit designed for low power, small size, and ease of use. The 1.6 W total power at 1 GSPS device is designed to sample wide bandwidth analog signals up to 400 mW per ADC channel 1.4 GHz. The AD9094 is optimized for wide input bandwidth, a SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) high sampling rate, high works linearity, and low power in a SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) small package. SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) The quad-ADC cores feature multistage, differential pipelined 0.9 V, 1.8 V, and 2.5 V dc supply operation architecture with integrated output error correction logic. Each No missing codes Internal ADC voltage reference ADC features wide bandwidth inputs that support a variety of Analog input buffer user-selectable input ranges. An integrated voltage reference On-chip dithering to improve small signal linearity facilitates design considerations. The analog inputs and clock Flexible differential input voltage range signals are differential inputs. 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) Users can configure each pair of intermediate frequency (IF) 1.4 GHz analog input full power bandwidth receiver outputs onto either one or two lanes of JESD204B Fast detect bits for efficient AGC implementation Subclass 1 or Subclass 0, high speed, serialized outputs, depending Differential clock input on the sample rate and the acceptable lane rate of the receiving Integer input clock divide by 1, 2, 4, or 8 logic device. Multiple device synchronization is supported through On-chip temperature diode the SYSREF, SYNCINBAB, and SYNCINBCD input pins. Flexible JESD204B lane configurations The AD9094 has flexible power-down options that allow APPLICATIONS significant power savings when desired. To program the power Laser imaging, detection, and ranging (LIDAR) down options, use the 1.8 V capable, serial port interface (SPI). Communications Digital oscilloscope (DSO) The AD9094 is available in a Pb-free, 72-lead, lead frame chip Ultrawideband satellite receivers scale package (LFCSP) and is specified over a junction Instrumentation temperature range of 40C to +105C. This product may be protected by one or more U.S. or international patents. Note that throughout this data sheet, multifunction pins, such as PDWN/STBY, are referred to either by the entire pin name or by a single function of the pin, for example, PDWN, when only that function is relevant. PRODUCT HIGHLIGHTS 1. Low power consumption per channel. 2. JESD204B lane rate support up to 15 Gbps. 3. Wide, full power bandwidth that supports IF sampling of signals up to 1.4 GHz. 4. Buffered inputs that ease filter design and implementation. 5. Programmable, fast overrange detection. 6. On-chip temperature diode for system thermal management. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9094 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Overview ................................................................. 31 Applications ...................................................................................... 1 JESD204B Link Establishment ................................................. 31 General Description ......................................................................... 1 PHY (Driver) Outputs ............................................................... 32 Product Highlights ........................................................................... 1 JESD204B Transmitter Converter Mapping .......................... 33 Revision History ............................................................................... 2 Configuring the JESD204B Link .............................................. 34 Functional Block Diagram .............................................................. 3 Latency ............................................................................................. 36 Specifications .................................................................................... 4 End to End Total Latency ......................................................... 36 DC Specifications ......................................................................... 4 Example Latency Calculations ................................................. 36 AC Specifications ......................................................................... 5 LMFC Referenced Latency ....................................................... 36 Digital Specifications ................................................................... 6 Deterministic Latency .................................................................... 37 Switching Specifications .............................................................. 7 Subclass 0 Operation ................................................................. 37 Timing Specifications .................................................................. 8 Subclass 1 Operation ................................................................. 37 Absolute Maximum Ratings ......................................................... 10 Multichip Synchronization ........................................................... 39 Thermal Resistance .................................................................... 10 Normal Mode ............................................................................. 39 ESD Caution................................................................................ 10 Timestamp Mode ....................................................................... 39 Pin Configuration and Function Descriptions .......................... 11 SYSREF Input ........................................................................... 41 Typical Performance Characteristics ........................................... 13 SYSREF Setup and Hold Window Monitor ........................ 42 Equivalent Circuits ......................................................................... 18 Test Modes ...................................................................................... 44 Theory of Operation ...................................................................... 20 ADC Test Modes ........................................................................ 44 ADC Architecture ...................................................................... 20 JESD204B Block Test Modes .................................................... 45 Analog Input Considerations ................................................... 20 SPI ..................................................................................................... 47 Voltage Reference ....................................................................... 21 Configuration Using the SPI .................................................... 47 DC Offset Calibration ................................................................ 22 Hardware Interface .................................................................... 47 Clock Input Considerations ...................................................... 22 SPI Accessible Features ............................................................. 47 ADC Overrange and Fast Detect .................................................. 25 Memory Map .................................................................................. 48 ADC Overrange .......................................................................... 25 Reading the Memory Map Register Table .............................. 48 Fast Threshold Detection (FD A, FD B, FD C, and FD D) Memory Map Register ............................................................... 49 ....................................................................................................... 25 Applications Information ............................................................. 66 Signal Monitor ................................................................................ 26 Power Supply Recommendations ............................................ 66 SPORT Over JESD204B ............................................................ 26 Exposed Pad Thermal Heat Slug Recommendations ........... 66 Digital Outputs ............................................................................... 29 AVDD1 SR (Pin 64) and AGND SR (Pin 63 and Pin 67) .. 66 Introduction to the JESD204B Interface ................................. 29 Outline Dimensions ....................................................................... 67 Setting Up the AD9094 Digital Interface ................................ 29 Ordering Guide .......................................................................... 67 REVISION HISTORY 10/2020Revision 0: Initial Version Rev. 0 Page 2 of 67