Low Power, 14-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator Data Sheet AD9102 The DDS is a 14-bit output, up to 180 MSPS master clock sine FEATURES wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB On-chip 4096 14-bit pattern memory frequency resolution. On-chip DDS Power dissipation 3.3 V, 4 mA output SRAM data can include directly generated stored waveforms, 96.54 mW 180 MSPS amplitude modulation patterns applied to DDS outputs, or DDS Sleep mode: <5 mW 3.3 V frequency tuning words. Supply voltage: 1.8 V to 3.3 V An internal pattern control state machine lets the user program SFDR to Nyquist the pattern period for the DAC as well the start delay within the 87 dBc 10 MHz output pattern period for the signal output on the DAC . Phase noise 1 kHz offset, 180 MSPS, 8 mA: 150 dBc/Hz A SPI interface is used to configure the digital waveform Differential current outputs: 8 mA max 3.3 V generator and load patterns into the SRAM. Small footprint, 32-lead, 5 mm 5 mm LFCSP with 3.6 mm 3.6 mm exposed paddle, and Pb-free package A gain adjustment factor and an offset adjustment are applied to the digital signal on their way into the DAC. APPLICATIONS The AD9102 offers exceptional ac and dc performance and Medical instrumentation supports DAC sampling rates of up to 180 MSPS. Portable instrumentation Signal generators, arbitrary waveform generators The flexible power supply operating range of 1.8 V to 3.3 V and Automotive radar low power dissipation of the AD9102 make it well suited for portable and low power applications. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9102 TxDAC and waveform generator is a high perfor- 1. High Integration. mance digital-to-analog converter (DAC) integrating on-chip On-chip DDS and 4096 14 pattern memory. pattern memory for complex waveform generation with a direct 2. Low Power. digital synthesizer (DDS). Power-down mode provides for low power idle periods. FUNCTIONAL BLOCK DIAGRAM 1V AD9102 SPI 10k AGND BAND INTERFACE START ADDR STOP ADDR GAP R SET1 START DELAY 16k DAC TRIGGER I REF TIMERS + STATE MACHINE 100A IOUTP DAC IOUTN GAIN OFFSET ADDRESS AVDD1 AVDD2 SRAM PHASE TUNING WORD DDS DDS DAC CLOCK 1.8V CLOCK LDO DIST 1.8V LDOs Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DAC CLOCK DVDD DLDO1 DLDO2 DGND SAWTOOTH CONSTANT RANDOM DDS SDIO SDO/SDI2/DOUT SCLK RESET CLKVDD CLDO REFIO CLKGND CAL SENSE CLKP CLKN FSADJ 11220-001 CSAD9102 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Current Outputs ........................................................... 19 Applications ....................................................................................... 1 Setting IOUTFS, DAC Gain ........................................................... 19 General Description ......................................................................... 1 Automatic IOUTFS Calibration ..................................................... 19 Product Highlights ........................................................................... 1 Clock Input .................................................................................. 20 Functional Block Diagram .............................................................. 1 DAC Output Clock Edge ........................................................... 21 Revision History ............................................................................... 2 Generating Signal Patterns ........................................................ 21 Specif icat ions ..................................................................................... 3 Pattern Generator Programming ............................................. 21 DC Specifications (3.3 V) ............................................................ 3 DAC Input Datapaths ................................................................ 22 DC Specifications (1.8 V) ............................................................ 4 DOUT Function ......................................................................... 22 Digital Timing Specifications (3.3 V) ........................................ 4 Direct Digital Synthesizer (DDS) ............................................. 23 Digital Timing Specifications (1.8 V) ........................................ 5 SRAM ........................................................................................... 23 Input/Output Signal Specifications ............................................ 5 Sawtooth Generator ................................................................... 23 AC Specifications (3.3 V) ............................................................ 6 Pseudo random Signal Generator ............................................ 24 AC Specifications (1.8 V) ............................................................ 6 DC Constant ............................................................................... 24 Power Supply Voltage Inputs and Power Dissipation .............. 7 Power Supply Notes ................................................................... 24 Absolute Maximum Ratings ............................................................ 8 Power Down Capabilities .......................................................... 24 Thermal Resistance ...................................................................... 8 Applications Information .............................................................. 25 ESD Caution .................................................................................. 8 Signal Generation Examples ..................................................... 25 Pin Configuration and Function Descriptions ............................. 9 Register Map ................................................................................... 26 Typical Performance Characteristics ........................................... 11 Register Descriptions ..................................................................... 28 Terminology .................................................................................... 16 Outline Dimensions ....................................................................... 36 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 36 SPI Port ........................................................................................ 18 DAC Transfer Function ............................................................. 19 REVISION HISTORY 5/2019Rev. 0 to Rev. A Changes to Table 26 ....................................................................... 31 Updated Outline Dimensions ....................................................... 36 Changes to Ordering Guide .......................................................... 36 1/2013Revision 0: Initial Version Rev. A Page 2 of 36