Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter AD9122 The AD9122 TxDAC+ includes features optimized for direct FEATURES conversion transmit applications, including complex digital mod- Flexible LVDS interface allows word, byte, or nibble load ulation, and gain and offset compensation. The DAC outputs Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF are optimized to interface seamlessly with analog quadrature Analog output: adjustable 8.7 mA to 31.7 mA, modulators, such as the ADL537x F-MOD series from Analog R = 25 to 50 L Devices, Inc. A 4-wire serial port interface provides for program- Integrated 2/4/8 interpolator/complex modulator allows ming/readback of many internal parameters. Full-scale output carrier placement anywhere in the DAC bandwidth current can be programmed over a range of 8.7 mA to 31.7 mA. Gain, dc offset, and phase adjustment for sideband The AD9122 comes in a 72-lead LFCSP. suppression Multiple chip synchronization interfaces PRODUCT HIGHLIGHTS High performance, low noise PLL clock multiplier 1. Ultralow noise and intermodulation distortion (IMD) Digital inverse sinc filter enable high quality synthesis of wideband signals from Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, baseband to high intermediate frequencies (IF). full operating conditions 2. Proprietary DAC output switching technique enhances 72-lead, exposed paddle LFCSP dynamic performance. 3. Current outputs are easily configured for various single- APPLICATIONS ended or differential circuit topologies. Wireless infrastructure 4. Flexible LVDS digital interface allows the standard 32-wire W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE bus to be reduced to one-half or one-quarter of the width. Digital high or low IF synthesis Transmit diversity COMPANION PRODUCTS Wideband communications: LMDS/MMDS, point-to-point IQ Modulators: ADL5370, ADL537x family GENERAL DESCRIPTION IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516, AD951x family The AD9122 is a dual, 16-bit, high dynamic range digital-to- Voltage Regulator Design Tool: ADIsimPower analog converter (DAC) that provides a sample rate of 1230 MSPS, Additional companion products on the AD9122 product page permitting multicarrier generation up to the Nyquist frequency. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF f LO f DC IF IF 2 2/4 I DAC SIN DIGITAL ANTIALIASING PA BASEBAND AQM FILTER PROCESSOR COS 2 2/4 Q DAC LO NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20092011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08281-001AD9122 TABLE OF CONTENTS Features .............................................................................................. 1 Data Rates vs. Interpolation Modes ......................................... 42 Applications ....................................................................................... 1 Coarse Modulation Mixing Sequences .................................... 42 General Description ......................................................................... 1 Quadrature Phase Correction ................................................... 43 Product Highlights ........................................................................... 1 DC Offset Correction ................................................................ 43 Companion Products ....................................................................... 1 Inverse Sinc Filter ....................................................................... 43 Typical Signal Chain ......................................................................... 1 DAC Input Clock Configurations ................................................ 44 Revision History ............................................................................... 3 Driving the DACCLK and REFCLK Inputs ........................... 44 Functional Block Diagram .............................................................. 4 Direct Clocking .......................................................................... 44 Specif icat ions ..................................................................................... 5 Clock Multiplication .................................................................. 44 DC Specifications ......................................................................... 5 PLL Settings ................................................................................ 45 Digital Specifications ................................................................... 6 Configuring the VCO Tuning Band ........................................ 45 Digital Input Data Timing Specifications ................................. 6 Analog Outputs............................................................................... 46 AC Specifications .......................................................................... 7 Transmit DAC Operation .......................................................... 46 Absolute Maximum Ratings ............................................................ 8 Auxiliary DAC Operation ......................................................... 47 Thermal Resistance ...................................................................... 8 Interfacing to Modulators ......................................................... 48 ESD Caution .................................................................................. 8 Baseband Filter Implementation .............................................. 48 Pin Configuration and Function Descriptions ............................. 9 Driving the ADL5375-15 .......................................................... 48 Typical Performance Characteristics ........................................... 11 Reducing LO Leakage and Unwanted Sidebands .................. 49 Terminology .................................................................................... 17 Device Power Management ........................................................... 50 Differences Between AD9122R1 and AD9122R2 ...................... 18 Power Dissipation....................................................................... 50 Device Marking of AD9122R1 and AD9122R2 ..................... 18 Temperature Sensor ................................................................... 51 Theory of Operation ...................................................................... 19 Multichip Synchronization ............................................................ 52 Serial Port Operation ................................................................. 19 Synchronization with Clock Multiplication ............................... 52 Data Format ................................................................................ 19 Synchronization with Direct Clocking .................................... 53 Serial Port Pin Descriptions ...................................................... 19 Data Rate Mode Synchronization ............................................ 53 Serial Port Options ..................................................................... 20 FIFO Rate Mode Synchronization ........................................... 54 Device Configuration Register Map and Descriptions ......... 21 Additional Synchronization Features ...................................... 55 LVDS Input Data Ports .................................................................. 32 Interrupt Request Operation ........................................................ 56 Word Interface Mode ................................................................. 32 Interrupt Service Routine .......................................................... 56 Byte Interface Mode ................................................................... 32 Interface Timing Validation .......................................................... 57 Nibble Interface Mode ............................................................... 32 SED Operation ............................................................................ 57 Interface Timing ......................................................................... 32 SED Example .............................................................................. 58 FIFO Operation .......................................................................... 33 Example Start-Up Routine ............................................................ 59 Digital Datapath .............................................................................. 36 Device Configuration ................................................................ 59 Premodulation ............................................................................ 36 Derived PLL Settings ................................................................. 59 Interpolation Filters ................................................................... 36 Derived NCO Settings ............................................................... 59 NCO Modulation ....................................................................... 39 Start-Up Sequence ...................................................................... 59 Datapath Configuration ............................................................ 39 Outline Dimensions ....................................................................... 60 Determining Interpolation Filter Modes ................................ 40 Ordering Guide .......................................................................... 60 Datapath Configuration Examples........................................... 41 Rev. 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