Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter AD9125 FEATURES GENERAL DESCRIPTION Flexible CMOS interface allows dual-word, word, or byte load The AD9125 is a dual, 16-bit, high dynamic range TxDAC+ Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF digital-to-analog converter (DAC) that provides a sample rate of Analog output: adjustable 8.7 mA to 31.7 mA, R = 25 to 50 L 1000 MSPS, permitting a multicarrier generation up to the Nyquist Novel 2/4/8 interpolator/complex modulator allows frequency. It includes features optimized for direct conversion carrier placement anywhere in the DAC bandwidth transmit applications, including complex digital modulation, Gain and phase adjustment for sideband suppression and gain and offset compensation. The DAC outputs are optimized Multichip synchronization interface to interface seamlessly with analog quadrature modulators, such High performance, low noise PLL clock multiplier as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire Digital inverse sinc filter serial port interface allows programming/readback of many inter- Low power: 900 mW at 500 MSPS, full operating conditions nal parameters. Full-scale output current can be programmed 72-lead, exposed paddle LFCSP over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP. APPLICATIONS PRODUCT HIGHLIGHTS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE 1. Ultralow noise and intermodulation distortion (IMD) Digital high or low IF synthesis enable high quality synthesis of wideband signals from Transmit diversity baseband to high intermediate frequencies. Wideband communications: LMDS/MMDS, point-to-point 2. A proprietary DAC output switching technique enhances Cable modem termination systems dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. The flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF f LO f DC IF IF I DAC 2 2/4 SIN DIGITAL ANTIALIASING BASEBAND PA AQM FILTER PROCESSOR COS 2 2/4 Q DAC LO NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09016-001AD9125 TABLE OF CONTENTS Features .............................................................................................. 1 NCO Modulation ....................................................................... 35 Applications ....................................................................................... 1 Datapath Configuration ............................................................ 35 General Description ......................................................................... 1 Determining Interpolation Filter Modes ................................ 36 Product Highlights ........................................................................... 1 Datapath Configuration Example ............................................ 37 Typical Signal Chain ......................................................................... 1 Data Rates vs. Interpolation Modes ......................................... 38 Revision History ............................................................................... 2 Coarse Modulation Mixing Sequences .................................... 38 Functional Block Diagram .............................................................. 3 Quadrature Phase Correction ................................................... 39 Specif icat ions ..................................................................................... 4 DC Offset Correction ................................................................ 39 DC Specifications ......................................................................... 4 Inverse Sinc Filter ....................................................................... 39 Digital Specifications ................................................................... 5 DAC Input Clock Configurations ................................................ 40 Latency and Power-Up Timing Specifications ......................... 5 DAC Input Clock Configurations ............................................ 40 AC Specifications .......................................................................... 6 Analog Outputs............................................................................... 42 Absolute Maximum Ratings ............................................................ 7 Transmit DAC Operation .......................................................... 42 Thermal Resistance ...................................................................... 7 Auxiliary DAC Operation ......................................................... 43 ESD Caution .................................................................................. 7 Baseband Filter Implementation .............................................. 44 Pin Configuration and Function Descriptions ............................. 8 Driving the ADL5375-15 .......................................................... 44 Typical Performance Characteristics ........................................... 10 Reducing LO Leakage and Unwanted Sidebands .................. 44 Terminology .................................................................................... 16 Device Power Dissipation .............................................................. 45 Theory of Operation ...................................................................... 17 Temperature Sensor ................................................................... 46 Serial Port Operation ................................................................. 17 Multichip Synchronization ............................................................ 47 Data Format ................................................................................ 17 Synchronization with Clock Multiplication ............................... 47 Serial Port Pin Descriptions ...................................................... 17 Synchronization with Direct Clocking .................................... 49 Serial Port Options ..................................................................... 18 Data Rate Mode Synchronization ............................................ 49 Device Configuration Register Map ............................................ 19 FIFO Rate Mode Synchronization ........................................... 50 Device Configuration Register Descriptions .......................... 21 Additional Synchronization Features ...................................... 51 CMOS Input Data Ports ................................................................ 29 Interrupt Request Operation ........................................................ 52 Dual-Word Mode ....................................................................... 29 Interrupt Service Routine .......................................................... 52 Word Mode ................................................................................. 29 Interface Timing Validation .......................................................... 53 Byte Mode .................................................................................... 29 SED Operation ............................................................................ 53 Interface Timing ......................................................................... 30 SED Example .............................................................................. 53 FIFO Operation .......................................................................... 30 Example Start-Up Routine ........................................................ 54 Digital Datapath .............................................................................. 32 Outline Dimensions ....................................................................... 55 Premodulation ............................................................................ 32 Ordering Guide .......................................................................... 55 Interpolation Filters ................................................................... 32 REVISION HISTORY 6/10Revision 0: Initial Version Rev. 0 Page 2 of 56