11-/14-Bit, 5.7 GSPS, RF Digital-to-Analog Converter Data Sheet AD9119/AD9129 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ I250U VREF DAC update rate: up to 5.7 GSPS Direct RF synthesis at 2.85 GSPS data rate AD9129 DC to 1.425 GHz in baseband mode SDIO 1.2V SDO SPI DC to 1.0 GHz in 2 interpolation mode CS SCLK 1.425 GHz to 4.2 GHz in Mix-Mode FRM x Bypassable 2 interpolation (FRAME/ PARITY) MIX- NORMAL MODE Excellent dynamic performance BASEBAND P0 D 13:0 P, MODE P0 D 13:0 N Supports DOCSIS 3.0 wideband ACLR/harmonic performance IOUTP Tx DAC 8 QAM carriers: ACLR > 65 dBc CORE DLL IOUTN DCI x Industry-leading single/multicarrier IF or RF synthesis 2 4-carrier W-CDMA ACLR at 2457.6 MSPS f = 900 MHz, ACLR = 71 dBc (baseband mode) P1 D 13:0 P, OUT PLL P1 D 13:0 N f = 2100 MHz, ACLR = 68 dBc (Mix-Mode) OUT f = 2700 MHz, ACLR = 67 dBc (Mix-Mode) OUT Dual-port LVDS and DHSTL data interface CLOCK DCR DCO x DISTRIBUTION Up to 1.425 GSPS operation Source synchronous DDR clocking with parity bit DACCLK x Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS) Figure 1. APPLICATIONS Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, LTE, point-to-point Instrumentation, automatic test equipment (ATE) Radar, jammers GENERAL DESCRIPTION The AD9119/AD9129 are high performance, 11-/14-bit RF digital- The AD9119/AD9129 include several features that may further to-analog converters (DACs) supporting data rates up to 2.85 simplify system integration. A dual-port, source synchronous GSPS. The DAC core is based on a quad-switch architecture that LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode integrity of the interface. On-chip delay locked loops (DLLs) or 2 interpolation. The high dynamic range and bandwidth optimize timing between different clock domains. enable multicarrier generation up to 4.2 GHz. A serial peripheral interface (SPI) configures the AD9119/ In baseband mode, wide bandwidth capability combines with high AD9129 and monitors the status of readback registers. The dynamic range to support from 1 to 158 contiguous carriers for AD9119/AD9129 are manufactured on a 0.18 m CMOS CATV infrastructure applications. A choice of two optional 2 process and operates from +1.8 V and 1.5 V supplies. It is interpolation filters is available to simplify the postreconstruction supplied in a 160-ball chip scale package ball grid array. filter by effectively increasing the DAC update rate by a factor of 2. PRODUCT HIGHLIGHTS In Mix-Mode operation, the AD9119/AD9129 can reconstruct 1. High dynamic range and signal reconstruction bandwidth RF carriers in the second and third Nyquist zone while still support RF signal synthesis of up to 4.2 GHz. maintaining exceptional dynamic range up to 4.2 GHz. The 2. Dual-port interface with double data rate (DDR) LVDS high performance NMOS DAC core features a quad-switch data receivers supports 2850 MSPS maximum conversion rate. architecture that enables industry-leading direct RF synthesis 3. Manufactured on a CMOS process a proprietary switching performance with minimal loss in output power. The output technique enhances dynamic performance. current can be programmed over a range of 9.5 mA to 34.4 mA. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2013-2017 Analog Devices, Inc. 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Technical Support www.analog.com LVDS DDR LVDS DDR RECEIVER RECEIVER 4 FIFO DATA ASSEMBLER DATA LATCH 11149-001AD9119/AD9129 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Peripheral Interface Pin Descriptions .......................... 36 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 37 Functional Block Diagram .............................................................. 1 Serial Port Configuration .......................................................... 37 General Description ......................................................................... 1 Theory of Operation ...................................................................... 38 Product Highlights ........................................................................... 1 LVDS Data Port Interface .......................................................... 39 Revision History ............................................................................... 2 Digital Datapath Description ................................................... 42 Specifications ..................................................................................... 3 Reset ............................................................................................. 47 DC Specifications ......................................................................... 3 Interrupt Requests ...................................................................... 47 LVDS Digital Specifications ........................................................ 4 Interface Timing Validation .......................................................... 48 HSTL Digital Specifications ........................................................ 4 Sample Error Detection (SED) Operation .............................. 48 Serial Port and CMOS Pin Specifications ................................. 5 SED Example............................................................................... 48 AC Specifications .......................................................................... 6 Analog Interface Considerations .................................................. 49 Absolute Maximum Ratings ............................................................ 7 Analog Modes of Operation ..................................................... 49 Thermal Resistance ...................................................................... 7 Clock Input.................................................................................. 50 ESD Caution .................................................................................. 7 PLL ............................................................................................... 50 Pin Configurations and Function Descriptions ........................... 8 Voltage Reference ....................................................................... 51 Typical Performance Characteristics ........................................... 12 Analog Outputs .......................................................................... 51 AD9119 ........................................................................................ 12 Start-Up Sequence ...................................................................... 54 AD9129 ........................................................................................ 22 Device Configuration Registers .................................................... 55 Terminology .................................................................................... 35 Device Configuration Register Map ........................................ 55 Serial Communications Port Overview ....................................... 36 Device Configuration Register Descriptions .......................... 56 Serial Peripheral Interface (SPI) ............................................... 36 Outline Dimensions ....................................................................... 66 General Operation of the SPI.................................................... 36 Ordering Guide .......................................................................... 66 Instruction Mode (8-Bit Instruction) ...................................... 36 REVISION HISTORY 6/2017Rev. A to Rev. B Changes to Figure 62, Figure 65, and Figure 67 ......................... 23 Changes to Table 8 ............................................................................ 9 Changes to Figure 76 and Figure 79 ............................................ 25 Changes to Figure 84, Figure 85, and Figure 87 ......................... 27 Changes to Table 9 .......................................................................... 11 Changes to Figure 87 ...................................................................... 27 Changes to Figure 90 and Figure 92 ............................................ 28 Added Reset Section ....................................................................... 47 Changes to Figure 95 and Figure 97 ............................................ 29 Changes to Figure 149 .................................................................... 51 Changes to Figure 118 ................................................................... 33 Changes to Figure 156 .................................................................... 53 Change to Serial Communications Port Overview Section .......... 36 Changes to Bits 2:1 Description, Table 29 ................................. 59 Changes to Theory of Operation Section.................................... 38 Change to Bit 5 Access, Table 37 .................................................. 61 Changes to LVDS Data Port Interface Section ........................... 39 Changes to Multiple DAC Synchronization Section ................. 44 9/2013Rev. 0 to Rev. A Change to PLL Section .................................................................. 50 Changes to Product Title ............................................................................ 1 Change to Voltage Reference Section .......................................... 51 Changes to Features Section and General Description Section ....... 1 Change to Register 0x01, Table 16 ............................................... 54 Changes to Table 1 ........................................................................... 3 Changes to Table 17 ....................................................................... 55 Changes to Table 2 and Table 3 ....................................................... 4 Changes to Bit 6, Table 37 ............................................................. 61 Changes to Dynamic Performance Parameter, Table 5 ............... 6 Changes to Table 49, Table 50, Table 51, and Table 52 .............. 63 Changes to Figure 10 and Figure 13 ............................................. 13 Changes to Table 53, Table 54, Table 55, Table 56, and Table 57 ... 64 Changes to Figure 21and Figure 23 .............................................. 15 Changes to Figure 24 and Figure 27 ............................................. 16 1/2013Revision 0: Initial Version Changes to Figure 35 and Figure 37 ............................................. 18 Rev. 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