Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converters Data Sheet AD9135/AD9136 FEATURES TYPICAL APPLICATION CIRCUIT QUAD MOD Support input data rate >2 GSPS LPF SYSREF ADRF6720 Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, 9 dBFS DAC Flexible 8-lane JESD204B interface 0/90 PHASE RF OUTPUT JESD204B SHIFTER Multiple chip synchronization Fixed latency DAC SYNCOUT0 Data generator latency compensation SYNCOUT1 AD9135/ AD9136 Selectable 1, 2, 4, or 8 interpolation filter LO IN MOD SPI Low power architecture CLK DAC Transmit enable function allows extra power saving and SPI instant control of the output status Figure 1. High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad APPLICATIONS Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point to point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range 1. Greater than 2 GHz, ultrawide complex signal bandwidth digital-to-analog converters (DACs) that provide a maximum enables emerging wideband and multiband wireless sample rate of 2800 MSPS, permitting a multicarrier generation applications. over a very wide bandwidth. The DAC outputs are optimized to 2. Advanced low spurious and distortion design techniques interface seamlessly with the ADRF6720, as well as other analog provide high quality synthesis of wideband signals from quadrature modulators (AQMs) from Analog Devices, Inc. An baseband to high intermediate frequencies. optional 3-wire or 4-wire serial port interface (SPI) provides for 3. JESD204B Subclass 1 support simplifies multichip programming/readback of many internal parameters. The full- synchronization in software and hardware design. scale output current can be programmed over a typical range of 4. Fewer pins for data interface width with a serializer/ 13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an deserializer (SERDES) JESD204B eight-lane interface. 88-lead LFCSP. 5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. 6. Small package size with 12 mm 12 mm footprint. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12578-001AD9135/AD9136 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Setup ......................................................................... 30 Applications ....................................................................................... 1 SERDES Clocks Setup ................................................................ 32 Typical Application Circuit ............................................................. 1 Equalization Mode Setup .......................................................... 32 General Description ......................................................................... 1 Link Latency Setup ..................................................................... 32 Product Highlights ........................................................................... 1 Crossbar Setup ............................................................................ 34 Revision History ............................................................................... 3 JESD204B Serial Data Interface .................................................... 35 Functional Block Diagram .............................................................. 4 JESD204B Overview .................................................................. 35 Specif icat ions ..................................................................................... 5 Physical Layer ............................................................................. 36 DC Specifications ......................................................................... 5 Data Link Layer .......................................................................... 39 Digital Specifications ................................................................... 6 Transport Layer .......................................................................... 48 Maximum DAC Update Rate Speed Specifications by Supply 7 JESD204B Test Modes ............................................................... 58 JESD204B Serial Interface Speed Specifications ...................... 7 JESD204B Error Monitoring ..................................................... 59 SYSREF Signal to DAC Clock Timing Specifications .............. 8 Hardware Considerations ......................................................... 61 Digital Input Data Timing Specifications ................................. 8 Digital Datapath ............................................................................. 65 Latency Variation Specifications ................................................ 9 DAC Paging ................................................................................. 65 JESD204B Interface Electrical Specifications ........................... 9 Data Format ................................................................................ 65 AC Specifications ........................................................................ 10 Interpolation Filters ................................................................... 65 Absolute Maximum Ratings .......................................................... 11 Inverse Sinc ................................................................................. 66 Thermal Resistance .................................................................... 11 Digital Gain, DC Offset, and Group Delay ............................. 66 ESD Caution ................................................................................ 11 Downstream Protection ............................................................ 68 Pin Configuration and Function Descriptions ........................... 12 Datapath PRBS ........................................................................... 69 Terminology .................................................................................... 15 DC Test Mode ............................................................................. 70 Typical Performance Characteristics ........................................... 16 Interrupt Request Operation ........................................................ 71 Theory of Operation ...................................................................... 22 Interrupt Service Routine .......................................................... 71 Serial Port Operation ..................................................................... 23 DAC Input Clock Configurations ................................................ 72 Data Format ................................................................................ 23 Driving the CLK Inputs .......................................................... 72 Serial Port Pin Descriptions ...................................................... 23 DAC PLL Fixed Register Writes ............................................... 72 Serial Port Options ..................................................................... 23 Clock Multiplication .................................................................. 72 Chip Information ............................................................................ 25 Starting the PLL .......................................................................... 74 Device Setup Guide ........................................................................ 26 Analog Outputs............................................................................... 75 O ver vie w ...................................................................................... 26 Transmit DAC Operation .......................................................... 75 Step 1: Start Up the DAC ........................................................... 26 Device Power Dissipation .............................................................. 78 Step 2: Digital Datapath ............................................................. 27 Temperature Sensor ................................................................... 78 Step 3: Transport Layer .............................................................. 27 Start-Up Sequence .......................................................................... 79 Step 4: Physical Layer ................................................................. 28 Step 1: Start Up the DAC ........................................................... 79 Step 5: Data Link Layer .............................................................. 28 Step 2: Digital Datapath ............................................................. 79 Step 6: Optional Error Monitoring .......................................... 29 Step 3: Transport Layer .............................................................. 80 Step 7: Optional Features ........................................................... 29 Step 4: Physical Layer ................................................................. 80 DAC PLL Setup ........................................................................... 30 Step 5: Data Link Layer .............................................................. 81 Interpolation ............................................................................... 30 Step 6: Error Monitoring ........................................................... 81 Rev. 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