16-Bit, 1600 MSPS, TxDAC+ Digital-to- Analog Converter Data Sheet AD9139 FEATURES GENERAL DESCRIPTION Selectable 1 or 2 interpolation filter The AD9139 is an 16-bit, high dynamic range digital-to-analog Support input signal bandwidth up to 575 MHz converter (DAC) that provides a sample rate of 1600 MSPS, Very small inherent latency variation: <2 DAC clock cycles permitting a multicarrier generation up to the Nyquist frequency. Proprietary low spurious and distortion design The AD9139 TxDAC+ includes features optimized for wideband 6-carrier GSM ACLR = 79 dBc at 200 MHz IF communication applications, including 1 and 2 interpolation, a SFDR >85 dBc (bandwidth = 300 MHz) at zero IF delay locked loop (DLL) powered high speed interface, sample Flexible 16-bit LVDS interface error detection, and parity detection. A 3-wire serial port interface Supports word and byte load provides for the programming/readback of many internal Multiple chip synchronization parameters. A full-scale output current can be programmed Fixed latency and data generator latency compensation over a range of 9 mA up to 33 mA. The AD9139 is available FIFO eases system timing and includes error detection in a 72-lead LFCSP. High performance, low noise PLL clock multiplier PRODUCT HIGHLIGHTS Digital inverse sinc filter 1. 575 MHz achievable input signal bandwidth. Low power: 700 mW at 1230 MSPS 2. Advanced low spurious and distortion design techniques 72-lead LFCSP provide high quality synthesis of wideband signals from APPLICATIONS baseband to high intermediate frequencies. Wireless communications: 3G/4G and MC-GSM base stations, 3. Very small inherent latency variation simplifies both software wideband repeaters, software defined radios and hardware design in the system. It allows easy multichip Wideband communications: point-to-point, LMDS/MMDS synchronization for most applications. Transmit diversity/MIMO 4. Low power architecture improves power efficiency. Instrumentation Automated test equipment FUNCTIONAL BLOCK DIAGRAM DLL DCIP/DCIN AD9139 13-TAP 16 DACOUTP D15P/D15N DAC 1 16-BIT DACOUTN HB1 2 DAC CLK D0P/D0N FRAMEP/PARITYP FRAMEN/PARITYN REF VREF AND 10 BIAS FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DACCLKP PROGRAMMING SERIAL POWER-ON MULTICHIP CLK REGISTERS INPUT/OUTPUT RESET SYNCHRONIZATION RCVR DACCLKN DAC CLK PORT REFP/SYNCP CLOCK REF SYNC MULTIPLIER RCVR REFN/SYNCN Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE CTRL LVDS DATA RECEIVER SED CTRL SED FIFO CTRL FIFO SDIO 8-SAMPLE SCLK INTERP CS MODE CTRL IRQ1 IRQ2 RESET TXEN INV SINC GAIN CONTROL DC OFFSET CONTROL GAIN 1 11744-001AD9139 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Multidevice Synchronization and Fixed Latency ....................... 29 Applications ....................................................................................... 1 Very Small Inherent Latency Variation ................................... 29 General Description ......................................................................... 1 Further Reducing the Latency Variation ................................. 29 Product Highlights ........................................................................... 1 Synchronization Implementation ............................................ 29 Functional Block Diagram .............................................................. 1 Synchronization Procedures ..................................................... 30 Revision History ............................................................................... 3 Interrupt Request Operation ........................................................ 32 Specifications ..................................................................................... 4 Interrupt Working Mechanism ................................................ 32 DC Specifications ......................................................................... 4 Interrupt Service Routine .......................................................... 32 Digital Specifications ................................................................... 5 Temperature Sensor ....................................................................... 33 Latency Variation Specifications ................................................ 6 DAC Input Clock Configurations ................................................ 34 AC Specifications .......................................................................... 6 Driving the DACCLK and REFCLK Inputs ........................... 34 Operating Speed Specifications .................................................. 6 Direct Clocking .......................................................................... 34 Absolute Maximum Ratings ....................................................... 7 Clock Multiplication .................................................................. 34 Thermal Resistance ...................................................................... 7 PLL Settings ................................................................................ 35 ESD Caution .................................................................................. 7 Configuring the VCO Tuning Band ........................................ 35 Pin Configuration and Function Descriptions ............................. 8 Automatic VCO Band Select .................................................... 35 Typical Performance Characteristics ........................................... 11 Manual VCO Band Select ......................................................... 35 Terminology .................................................................................... 15 PLL Enable Sequence ................................................................. 35 Serial Port Operation ..................................................................... 16 Analog Outputs............................................................................... 36 Data Format ................................................................................ 16 Transmit DAC Operation .......................................................... 36 Serial Port Pin Descriptions ...................................................... 16 Interfacing to Modulators ......................................................... 37 Serial Port Options ..................................................................... 16 Reducing LO Leakage and Unwanted Sidebands .................. 38 Data Interface .................................................................................. 18 Start-Up Routine ............................................................................ 39 LVDS Input Data Ports .............................................................. 18 Device Configuration Register Map and Description ............... 40 Word Interface Mode ................................................................. 18 SPI Configure Register .............................................................. 42 Byte Interface Mode ................................................................... 18 Power-Down Control Register ................................................. 42 Data Interface Configuration Options .................................... 18 Interrupt Enable 0 Register ....................................................... 42 DLL Interface Mode ................................................................... 18 Interrupt Enable 1 Register ....................................................... 42 Parity ............................................................................................ 21 Interrupt Flag 0 Register ............................................................ 43 SED Operation ............................................................................ 21 Interrupt Flag 1 Register ............................................................ 43 SED Example ............................................................................... 22 Interrupt Select 0 Register ......................................................... 43 Delay Line Interface Mode ........................................................ 22 Interrupt Select 1 Register ......................................................... 44 FIFO Operation .............................................................................. 24 Frame Mode Register ................................................................. 44 Resetting the FIFO ..................................................................... 25 Data Control 0 Register ............................................................. 44 Serial Port Initiated FIFO Reset ............................................... 25 Data Control 1 Register ............................................................. 44 Frame Initiated FIFO Reset ....................................................... 25 Data Control 2 Register ............................................................. 45 Digital Datapath .............................................................................. 27 Data Control 3 Register ............................................................. 45 Interpolation Filters ................................................................... 27 Data Status 0 Register ................................................................ 45 Inverse Sinc Filter ....................................................................... 28 DAC Clock Receiver Control Register .................................... 46 Digital Function Configuration ................................................ 28 Reference Clock Receiver Control Register ............................ 46 Rev. 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