Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9142A FEATURES GENERAL DESCRIPTION Supports input data rate up to 575 MHz The AD9142A is a dual, 16-bit, high dynamic range digital-to- Very small inherent latency variation: <2 DAC clock cycles analog converter (DAC) that provides a sample rate of 1600 MSPS, Proprietary low spurious and distortion design permitting a multicarrier generation up to the Nyquist frequency. 6-carrier GSM ACLR = 79 dBc at 200 MHz IF The AD9142A TxDAC+ includes features optimized for direct SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF conversion transmit applications, including complex digital mod- Flexible 16-bit LVDS interface ulation, input signal power detection, and gain, phase, and offset Supports word and byte load compensation. The DAC outputs are optimized to interface seam- Data interface DLL lessly with analog quadrature modulators, such as the ADL537x Sample error detection and parity F-MOD series and the ADRF670x series from Analog Devices, Multiple chip synchronization Inc. A 3-wire serial port interface provides for the programming/ Fixed latency and data generator latency compensation readback of many internal parameters. Full-scale output current Selectable 2, 4, 8 interpolation filter can be programmed over a range of 9 mA to 33 mA. The Low power architecture AD9142A is available in a 72-lead LFCSP. f /4 power saving coarse mixer S PRODUCT HIGHLIGHTS Input signal power detection 1. Wide signal bandwidth (BW) enables emerging wideband Emergency stop for downstream analog circuitry and multiband wireless applications. protection 2. Advanced low spurious and distortion design techniques FIFO error detection provide high quality synthesis of wideband signals from On-chip numeric control oscillator allows carrier placement baseband to high intermediate frequencies. anywhere in the DAC Nyquist bandwidth 3. Very small inherent latency variation simplifies both software Transmit enable function for extra power saving and hardware design in the system. It allows easy multichip High performance, low noise PLL clock multiplier Digital gain and phase adjustment for sideband suppression synchronization for most applications. Digital inverse sinc filter 4. New low power architecture improves power efficiency Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full (mW/MHz/channel) by 30%. operating conditions 5. Input signal power and FIFO error detection simplify 72-lead LFCSP designs for downstream analog circuitry protection. 6. Programmable transmit enable function allows easy design APPLICATIONS balance between power consumption and wakeup time. Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9142A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Datapath Configuration ............................................................ 35 Applications ....................................................................................... 1 Digital Quadrature Gain and Phase Adjustment ................... 35 General Description ......................................................................... 1 DC Offset Adjustment ............................................................... 35 Product Highlights ........................................................................... 1 Inverse Sinc Filter ....................................................................... 36 Revision History ............................................................................... 4 Input Signal Power Detection and Protection ........................ 36 Functional Block Diagram .............................................................. 5 Transmit Enable Function ......................................................... 37 Specifications ..................................................................................... 6 Digital Function Configuration ............................................... 37 DC Specifications ......................................................................... 6 Multidevice Synchronization and Fixed Latency ....................... 38 Digital Specifications ................................................................... 8 Very Small Inherent Latency Variation ................................... 38 DAC Latency Specifications ........................................................ 9 Further Reducing the Latency Variation ................................. 38 Latency Variation Specifications ................................................ 9 Synchronization Implementation ............................................ 39 AC Specifications ........................................................................ 10 Synchronization Procedures ..................................................... 39 Operating Speed Specifications ................................................ 10 Interrupt Request Operation ........................................................ 40 Absolute Maximum Ratings ..................................................... 11 Interrupt Working Mechanism ................................................ 40 Thermal Resistance .................................................................... 11 Interrupt Service Routine .......................................................... 40 ESD Caution ................................................................................ 11 Temperature Sensor ....................................................................... 41 Pin Configuration and Function Descriptions ........................... 12 DAC Input Clock Configurations ................................................ 42 Typical Performance Characteristics ........................................... 15 Driving the DACCLK and REFCLK Inputs ........................... 42 Terminology .................................................................................... 20 Direct Clocking .......................................................................... 42 Serial Port Operation ..................................................................... 21 Clock Multiplication .................................................................. 42 Data Format ................................................................................ 21 PLL Settings ................................................................................ 43 Serial Port Pin Descriptions ...................................................... 21 Configuring the VCO Tuning Band ........................................ 43 Serial Port Options ..................................................................... 21 Automatic VCO Band Select .................................................... 43 Data Interface .................................................................................. 23 Manual VCO Band Select ......................................................... 43 LVDS Input Data Ports .............................................................. 23 PLL Enable Sequence ................................................................. 43 Word Interface Mode ................................................................. 23 Analog Outputs............................................................................... 44 Byte Interface Mode ................................................................... 23 Transmit DAC Operation .......................................................... 44 Data Interface Configuration Options .................................... 23 Interfacing to Modulators ......................................................... 45 DLL Interface Mode ................................................................... 23 Reducing LO Leakage and Unwanted Sidebands .................. 46 Parity ............................................................................................ 26 Example Start-Up Routine ............................................................ 47 SED Operation ............................................................................ 26 Device Configuration and Start-Up Sequence 1 .................... 47 SED Example ............................................................................... 27 Device Configuration and Start-Up Sequence 2 .................... 47 Delay Line Interface Mode ........................................................ 27 Device Configuration Register Map and Description ............... 49 FIFO Operation .............................................................................. 29 SPI Configure Register .............................................................. 52 Resetting the FIFO ..................................................................... 30 Power-Down Control Register ................................................. 52 Serial Port Initiated FIFO Reset ............................................... 30 Interrupt Enable0 Register ........................................................ 52 Frame Initiated FIFO Reset ....................................................... 30 Interrupt Enable1 Register ........................................................ 53 Digital Datapath .............................................................................. 32 Interrupt Flag0 Register ............................................................. 53 Interpolation Filters ................................................................... 32 Interrupt Flag1 Register ............................................................. 53 Digital Modulation ..................................................................... 34 Interrupt Select0 Register .......................................................... 54 Rev. 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