Quad, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9144 FEATURES TYPICAL APPLICATION CIRCUIT Supports input data rate >1 GSPS QUAD MOD LPF ADRF6720 Proprietary low spurious and distortion design DAC 6-carrier GSM IMD = 77 dBc at 75 MHz IF 0/90 PHASE SFDR = 82 dBc at dc IF, 9 dBFS JESD204B SHIFTER SYNCOUTx Flexible 8-lane JESD204B interface DAC SYSREF Support quad or dual DAC mode at 2.8 GSPS Multiple chip synchronization AD9144 Fixed latency LO IN MOD SPI QUAD Data generator latency compensation DAC QUAD MOD LPF Selectable 1, 2, 4, 8 interpolation filter ADRF6720 DAC Low power architecture Input signal power detection 0/90 PHASE JESD204B SHIFTER Emergency stop for downstream analog circuitry protection SYNCOUTx DAC Transmit enable function allows extra power saving High performance, low noise phase-locked loop (PLL) clock multiplier LO IN MOD SPI CLK DAC Digital inverse sinc filter SPI Low power: 1.6 W at 1.6 GSPS, 1.7 W at 2.0 GSPS, Figure 1. full operating conditions 88-lead LFCSP with exposed pad APPLICATIONS Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point-to-point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) PRODUCT HIGHLIGHTS Instrumentation Automated test equipment 1. Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless GENERAL DESCRIPTION applications. The AD9144 is a quad, 16-bit, high dynamic range digital-to- 2. Advanced low spurious and distortion design techniques analog converter (DAC) that provides a maximum sample rate provide high quality synthesis of wideband signals from of 2.8 GSPS, permitting a multicarrier generation up to the baseband to high intermediate frequencies. Nyquist frequency. The DAC outputs are optimized to interface 3. JESD204B Subclass 1 support simplifies multichip seamlessly with the ADRF6720 analog quadrature modulator synchronization in software and hardware design. (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire 4. Fewer pins for data interface width with a serializer/ serial port interface (SPI) provides for programming/readback deserializer (SERDES) JESD204B eight-lane interface. of many internal parameters. Full-scale output current can be 5. Programmable transmit enable function allows easy design programmed over a typical range of 13.9 mA to 27.0 mA. The balance between power consumption and wake-up time. AD9144 is available in an 88-lead LFCSP. 6. Small package size with 12 mm 12 mm footprint. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11675-001AD9144 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Setup ......................................................................... 30 Applications ....................................................................................... 1 SERDES Clocks Setup ................................................................ 32 General Description ......................................................................... 1 Equalization Mode Setup .......................................................... 32 Typical Application Circuit ............................................................. 1 Link Latency Setup ..................................................................... 32 Product Highlights ........................................................................... 1 Crossbar Setup ............................................................................ 34 Revision History ............................................................................... 3 JESD204B Serial Data Interface .................................................... 35 Functional Block Diagram .............................................................. 5 JESD204B Overview .................................................................. 35 Specif icat ions ..................................................................................... 6 Physical Layer ............................................................................. 36 DC Specifications ......................................................................... 6 Data Link Layer .......................................................................... 39 Digital Specifications ................................................................... 7 Transport Layer .......................................................................... 48 Maximum DAC Update Rate Speed Specifications by Supply ..... 8 JESD204B Test Modes ............................................................... 61 JESD204B Serial Interface Speed Specifications ...................... 8 JESD204B Error Monitoring ..................................................... 62 SYSREF to DAC Clock Timing Specifications ......................... 9 Hardware Considerations ......................................................... 64 Digital Input Data Timing Specifications ................................. 9 Digital Datapath ............................................................................. 68 Latency Variation Specifications .............................................. 10 Dual Paging ................................................................................. 68 JESD204B Interface Electrical Specifications ......................... 10 Data Format ................................................................................ 68 AC Specifications ........................................................................ 11 Interpolation Filters ................................................................... 68 Absolute Maximum Ratings .......................................................... 12 Digital Modulation ..................................................................... 69 Thermal Resistance .................................................................... 12 Inverse Sinc ................................................................................. 70 ESD Caution ................................................................................ 12 Digital Gain, Phase Adjust, DC Offset, and Group Delay .... 70 Pin Configuration and Function Descriptions ........................... 13 I to Q Swap .................................................................................. 71 Terminology .................................................................................... 16 NCO Alignment ......................................................................... 71 Typical Performance Characteristics ........................................... 17 Downstream Protection ............................................................ 73 Theory of Operation ...................................................................... 22 Datapath PRBS ........................................................................... 75 Serial Port Operation ..................................................................... 23 DC Test Mode ............................................................................. 75 Data Format ................................................................................ 23 Interrupt Request Operation ........................................................ 76 Serial Port Pin Descriptions ...................................................... 23 Interrupt Service Routine .......................................................... 76 Serial Port Options ..................................................................... 23 DAC Input Clock Configurations ................................................ 77 Chip Information ............................................................................ 25 Driving the CLK Inputs .......................................................... 77 Device Setup Guide ........................................................................ 26 DAC PLL Fixed Register Writes ............................................... 77 O ver vie w ...................................................................................... 26 Clock Multiplication .................................................................. 77 Step 1: Start Up the DAC ........................................................... 26 Starting the PLL .......................................................................... 79 Step 2: Digital Datapath ............................................................. 27 Analog Outputs............................................................................... 80 Step 3: Transport Layer .............................................................. 27 Transmit DAC Operation .......................................................... 80 Step 4: Physical Layer ................................................................. 28 Device Power Dissipation .............................................................. 83 Step 5: Data Link Layer .............................................................. 28 Temperature Sensor ................................................................... 83 Step 6: Optional Error Monitoring .......................................... 29 Start-Up Sequence .......................................................................... 84 Step 7: Optional Features ........................................................... 29 Step 1: Start Up the DAC ........................................................... 84 DAC PLL Setup ........................................................................... 30 Step 2: Digital Datapath ............................................................. 84 Interpolation ............................................................................... 30 Step 3: Transport Layer .............................................................. 85 Rev. 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