Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9146 The AD9146 TxDAC+ includes features optimized for direct FEATURES conversion transmit applications, including complex digital mod- Flexible LVDS interface allows byte or nibble load ulation, and gain and offset compensation. The DAC outputs Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF are optimized to interface seamlessly with analog quadrature Analog output: adjustable 8.7 mA to 31.7 mA, R = 25 to 50 L modulators, such as the ADL537x F-MOD series from Analog Integrated 2/4 interpolator/complex modulator allows Devices, Inc. A 3-wire serial port interface provides for program- carrier placement anywhere in the DAC bandwidth ming/readback of many internal parameters. Full-scale output Gain, dc offset, and phase adjustment for sideband current can be programmed over a range of 8.7 mA to 31.7 mA. suppression The AD9146 comes in a 48-lead LFCSP. Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier PRODUCT HIGHLIGHTS Digital inverse sinc filter 1. Ultralow noise and intermodulation distortion (IMD) Low power: 1.2 W at 1.0 GSPS, 800 mW at 500 MSPS, enable high quality synthesis of wideband signals from full operating conditions baseband to high intermediate frequencies (IF). 48-lead, exposed paddle LFCSP 2. Proprietary DAC output switching technique enhances APPLICATIONS dynamic performance. 3. Current outputs are easily configured for various single- Wireless infrastructure ended or differential circuit topologies. W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE 4. Compact LVDS digital interface offers reduced width Digital high or low IF synthesis data bus. Transmit diversity Wideband communications: LMDS/MMDS, point-to-point COMPANION PRODUCTS GENERAL DESCRIPTION IQ Modulators: ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family The AD9146 is a dual, 16-bit, high dynamic range digital-to- Clock Drivers: AD9516, AD951x family analog converter (DAC) that provides a sample rate of 1000 MSPS Voltage Regulator Design Tool: ADIsimPower with nominal supplies and 1230 MSPS with increased supplies, Additional companion products on the AD9146 product page permitting multicarrier generation up to the Nyquist frequency. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF f LO f DC IF IF OFFSET 1 2/4 AND SINC I DAC GAIN ADJ DIGITAL ANTIALIASING PA BASEBAND AQM FILTER PROCESSOR OFFSET 1 2/4 AND SINC Q DAC LO GAIN ADJ NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20112012 Analog Devices, Inc. All rights reserved. 09691-001AD9146 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DC Offset Correction ................................................................ 35 Applications ....................................................................................... 1 Inverse Sinc Filter ....................................................................... 36 General Description ......................................................................... 1 DAC Input Clock Configurations ................................................ 37 Product Highlights ........................................................................... 1 Driving the DACCLK and REFCLK Inputs ........................... 37 Companion Products ....................................................................... 1 Direct Clocking .......................................................................... 37 Typical Signal Chain......................................................................... 1 Clock Multiplication .................................................................. 37 Revision History ............................................................................... 3 PLL Settings ................................................................................ 38 Functional Block Diagram .............................................................. 4 Configuring the VCO Tuning Band ........................................ 38 Specifications ..................................................................................... 5 Analog Outputs............................................................................... 39 DC Specifications ......................................................................... 5 Transmit DAC Operation .......................................................... 39 Digital Specifications ................................................................... 6 Auxiliary DAC Operation ......................................................... 40 Digital Input Data Timing Specifications ................................. 6 Interfacing to Modulators ......................................................... 41 AC Specifications .......................................................................... 7 Baseband Filter Implementation .............................................. 41 Absolute Maximum Ratings ............................................................ 8 Driving the ADL5375-15 .......................................................... 41 Thermal Resistance ...................................................................... 8 Reducing LO Leakage and Unwanted Sidebands .................. 42 ESD Caution .................................................................................. 8 Device Power Management........................................................... 43 Pin Configuration and Function Descriptions ............................. 9 Power Dissipation....................................................................... 43 Typical Performance Characteristics ........................................... 11 Tx Enable ..................................................................................... 43 Terminology .................................................................................... 15 Temperature Sensor ................................................................... 44 Theory of Operation ...................................................................... 16 Multichip Synchronization ............................................................ 45 Serial Port Operation ................................................................. 16 Synchronization with Clock Multiplication ............................... 45 Data Format ................................................................................ 16 Synchronization with Direct Clocking .................................... 46 Serial Port Pin Descriptions ...................................................... 16 Data Rate Mode Synchronization ............................................ 46 Serial Port Options ..................................................................... 17 FIFO Rate Mode Synchronization ........................................... 47 Device Configuration Register Map and Descriptions ......... 18 Additional Synchronization Features ...................................... 48 LVDS Input Data Ports .................................................................. 28 Interrupt Request Operation ........................................................ 49 Byte Interface Mode ................................................................... 28 Interrupt Service Routine .......................................................... 49 Nibble Interface Mode ............................................................... 28 Interface Timing Validation .......................................................... 50 FIFO Operation .......................................................................... 28 SED Operation ............................................................................ 50 Interface Timing ......................................................................... 31 SED Example............................................................................... 51 Digital Datapath .............................................................................. 32 Example Start-Up Routine ............................................................ 52 Premodulation ............................................................................ 32 Device Configuration ................................................................ 52 Interpolation Filters.................................................................... 32 Derived PLL Settings ................................................................. 52 Datapath Configuration ............................................................ 34 Start-Up Sequence ...................................................................... 52 Determining Interpolation Filter Modes ................................ 34 Outline Dimensions ....................................................................... 53 Coarse Modulation Mixing Sequences .................................... 35 Ordering Guide .......................................................................... 53 Quadrature Phase Correction ................................................... 35 Rev. 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