Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9148 FEATURES GENERAL DESCRIPTION Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF The AD9148 is a quad, 16-bit, high dynamic range, digital-to- Channel-to-channel isolation > 90 dB analog converter (DAC) that provides a sample rate of 1000 MSPS. Analog output This device includes features optimized for direct conversion Adjustable 8.7 mA to 31.7 mA transmit applications, including gain, phase, and offset compen- R = 25 to 50 L sation. The DAC outputs are optimized to interface seamlessly with Novel 2, 4, and 8 interpolator eases data interface analog quadrature modulators such as the ADL5371/ADL5372/ On-chip fine complex NCO allows carrier placement ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI) anywhere in DAC bandwidth is provided for programming of the internal device parameters. High performance, low noise PLL clock multiplier Full-scale output current can be programmed over a range of 8.7 mA Multiple chip synchronization interface to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies Programmable digital inverse sinc filter for a total power consumption of 3 W at the maximum sample Auxiliary DACs allow for offset control rate. The AD9148 is enclosed in a 196-ball chip scale package ball Gain DACs allow for I and Q gain matching grid array with the option of an attached heat spreader. Programmable I and Q phase compensation PRODUCT HIGHLIGHTS Digital gain control 1. Low noise and intermodulation distortion (IMD) enable Flexible LVDS digital I/F supports 32- or 16-bit bus width high quality synthesis of wideband signals from baseband 196-ball CSP BGA, 12 mm 12 mm to high intermediate frequencies. APPLICATIONS 2. A proprietary DAC output switching technique enhances Wireless infrastructure dynamic performance. LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM 3. The current outputs are easily configured for various MIMO/transmit diversity single-ended or differential circuit topologies. Digital high or low IF synthesis 4. The LVDS data input interface includes FIFO to ease input timing. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF LO f f IF IF DC DIGITAL INTERPOLATION FILTERS 2 2 2 DAC1 POST DAC AQM PA ANALOG FILTER LO 2 2 2 DAC2 FPGA/ASIC/DSP 2 2 2 DAC3 LO POST DAC AQM PA 2 2 2 DAC4 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 08910-001AD9148 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Synchronizing Multiple Devices .............................................. 45 Applications ....................................................................................... 1 Synchronization with Clock Multiplication ............................... 45 General Description ......................................................................... 1 Synchronization with Direct Clocking .................................... 47 Product Highlights ........................................................................... 1 Additional Synchronization Features ...................................... 48 Typical Signal Chain ......................................................................... 1 Interface Timing ............................................................................. 49 Revision History ............................................................................... 3 Digital Data Path ............................................................................ 50 Functional Block Diagram .............................................................. 4 Premodulation ............................................................................ 50 Specifications ..................................................................................... 5 Programmable Inverse Sinc Filter ............................................ 50 DC Specifications ......................................................................... 5 Interpolation Filters ................................................................... 51 Input/Output Signal Specifications ............................................ 6 Fine Modulation ......................................................................... 54 Digital Input Data Timing Specifications ................................. 7 Quadrature Phase Correction ................................................... 55 AC Specifications .......................................................................... 8 DC Offset Correction ................................................................ 55 Absolute Maximum Ratings ............................................................ 9 Digital Gain Control .................................................................. 55 Thermal Resistance ...................................................................... 9 Clock Generation ........................................................................... 56 Maximum Safe Power Dissipation ............................................. 9 DAC Input Clock Configurations ............................................ 56 ESD Caution .................................................................................. 9 Driving the CLK x and REFCLK x Inputs ............................ 56 Pin Configurations and Function Descriptions ......................... 11 Direct Clocking .......................................................................... 56 Typical Performance Characteristics ........................................... 15 Clock Multiplication .................................................................. 57 Terminology .................................................................................... 21 Analog Outputs............................................................................... 59 Serial Peripheral Interface ............................................................. 22 Transmit DAC Operation .......................................................... 59 General Operation of the Serial Interface ............................... 22 Auxiliary DAC Operation ......................................................... 60 Data Format ................................................................................ 22 Interfacing to Modulators ......................................................... 61 SPI Pin Descriptions .................................................................. 22 Device Power Dissipation .............................................................. 63 SPI Options ................................................................................. 23 Temperature Sensor ....................................................................... 65 SPI Register Map ............................................................................. 24 Interrupt Request Operation ........................................................ 66 SPI Register Descriptions .......................................................... 26 Interrupt Service Routine .......................................................... 66 Input Data Ports .............................................................................. 40 Interface Timing Validation .......................................................... 67 Dual-Port Mode .......................................................................... 40 SED Operation ............................................................................ 67 Single-Port Mode ........................................................................ 40 SED Example .............................................................................. 67 Byte Mode .................................................................................... 41 Example Start-Up Routine ............................................................ 68 Data Interface Options .............................................................. 41 Derived PLL Settings ................................................................. 68 Recommended Frame Input Bias Circuitry ............................ 41 Derived NCO Settings ............................................................... 68 FIFO Operation .............................................................................. 42 Start-Up Sequence ...................................................................... 68 Synchronizing and Resetting the FIFO ................................... 43 Device Verification Sequence ................................................... 68 Monitoring the FIFO Status ...................................................... 44 Outline Dimensions ....................................................................... 69 Device Synchronization ................................................................. 45 Ordering Guide .......................................................................... 70 Rev. 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