Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9152 FEATURES GENERAL DESCRIPTION Supports input data rates up to 1.125 GSPS The AD9152 is a dual, 16-bit, high dynamic range digital-to- Proprietary low spurious and distortion design analog converter (DAC) that provides a maximum sample rate of Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc 2.25 GSPS, permitting a multicarrier generation up to the Nyquist at 180 MHz IF frequency. The DAC outputs are optimized to interface seam- SFDR = 72 dBc at 150 MHz IF, 6 dBFS lessly with the ADRF6720 analog quadrature modulator (AQM) Flexible 4-lane JESD204B interface from Analog Devices, Inc. An optional 3-wire or 4-wire serial Multiple chip synchronization port interface (SPI) provides for programming/readback of Fixed latency many internal parameters. The full-scale output current can be Data generator latency compensation programmed over a range of 4 mA to 20 mA. The AD9152 is Selectable 1, 2, 4, and 8 interpolation filter available in a 56-lead LFCSP. The AD9152 is a member of the Low power architecture TxDAC+ family. Input signal power detection PRODUCT HIGHLIGHTS Emergency stop for downstream analog circuitry protection 1. Ultrawide signal bandwidth enables emerging wideband Transmit enable function allows extra power saving and multiband wireless applications. High performance, low noise, phase-locked loop (PLL) clock 2. Advanced low spurious and distortion design techniques multiplier provide high quality synthesis of wideband signals from Digital inverse sinc filter and programmable finite impulse baseband to high intermediate frequencies. response (FIR) filter 3. JESD204B Subclass 1 support simplifies multichip Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full synchronization in software and hardware design. operating conditions 4. Fewer pins for data interface width with the serializer/ 56-lead LFCSP with exposed pad deserializer (SERDES) JESD204B four-lane interface. APPLICATIONS 5. Programmable transmit enable function allows easy design Wireless communications balance between power consumption and wake-up time. Multicarrier LTE and GSM base stations 6. Small package size with an 8 mm 8 mm footprint. Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment FUNCTIONAL BLOCK DIAGRAM QUAD MOD DUAL CTRL LPF ADRF6720 DAC DAC RF 0/90 PHASE AMP AMP JESD204B OUTPUT SHIFTER SYNC VGA SYSREF DAC AD9152 LO IN MOD SPI DAC SPI Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12994-001AD9152 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interpolation ............................................................................... 27 Applications ....................................................................................... 1 JESD204B Setup ......................................................................... 27 General Description ......................................................................... 1 SERDES Clocks Setup ................................................................ 28 Product Highlights ........................................................................... 1 Equalization Mode Setup .......................................................... 28 Functional Block Diagram .............................................................. 1 Link Latency Setup ..................................................................... 28 Revision History ............................................................................... 3 Crossbar Setup ............................................................................ 30 Detailed Functional Block Diagram .............................................. 4 JESD204B Serial Data Interface .................................................... 31 Specifications ..................................................................................... 5 JESD204B Overview .................................................................. 31 DC Specifications ......................................................................... 5 Physical Layer ............................................................................. 32 Digital Specifications ................................................................... 6 Data Link Layer .......................................................................... 35 Maximum DAC Update Rate Speed Specifications by Transport Layer .......................................................................... 43 Supply ............................................................................................. 7 JESD204B Test Modes ............................................................... 51 JESD204B Serial Interface Speed Specifications ...................... 7 JESD204B Error Monitoring..................................................... 52 SYSREF to DAC Clock Timing Specifications ....................... 8 Digital Datapath ............................................................................. 54 Digital Input Data Timing Specifications ................................. 8 Data Format ................................................................................ 54 Latency Variation Specifications ................................................ 9 Interpolation Filters ................................................................... 54 JESD204B Interface Electrical Specifications ........................... 9 Digital Modulation ..................................................................... 55 AC Specifications ........................................................................ 10 NCO Alignment ......................................................................... 56 Absolute Maximum Ratings .......................................................... 11 Inverse Sinc ................................................................................. 57 Thermal Resistance .................................................................... 11 Programmable FIR Filter (PFIR) ............................................. 57 ESD Caution ................................................................................ 11 Digital Gain, Phase Adjust, DC Offset, and Coarse Group Pin Configuration and Function Descriptions ........................... 12 Delay ............................................................................................ 57 Terminology .................................................................................... 14 Downstream Protection ............................................................ 59 Typical Performance Characteristics ........................................... 15 Datapath PRBS ........................................................................... 61 Theory of Operation ...................................................................... 20 DC Test Mode ............................................................................. 62 Serial Port Operation ..................................................................... 21 Interrupt Request Operation ........................................................ 63 Data Format ................................................................................ 21 Interrupt Service Routine .......................................................... 63 Serial Port Pin Descriptions ...................................................... 21 DAC Input Clock Configurations ................................................ 64 Serial Port Options ..................................................................... 21 Driving the DACCLK AND REFCLK Inputs ................... 64 Chip Information ............................................................................ 23 Condition Specific Register Writes .......................................... 64 Device Setup Guide ........................................................................ 24 Starting the PLL .......................................................................... 65 Overview ...................................................................................... 24 Analog Outputs............................................................................... 67 Step 1: Start Up the DAC ........................................................... 24 Transmit DAC Operation .......................................................... 67 Step 2: Digital Datapath ............................................................. 25 Temperature Sensor ....................................................................... 68 Step 3: Transport Layer .............................................................. 25 Example Start-Up Sequence .......................................................... 69 Step 4: Physical Layer ................................................................. 26 Step 1: Start Up the DAC ........................................................... 69 Step 5: Data Link Layer .............................................................. 26 Step 2: Digital Datapath ............................................................. 70 Step 6: Optional Error Monitoring .......................................... 26 Step 3: Transport Layer .............................................................. 70 Step 7: Optional Features ........................................................... 26 Step 4: Physical Layer ................................................................. 70 DAC PLL Setup ........................................................................... 27 Step 5: Data Link Layer .............................................................. 70 Rev. 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