Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9154 FEATURES FUNCTIONAL BLOCK DIAGRAM QUAD MOD Supports input data rates up to 1.096 GSPS ADRF6720-27 Proprietary, low spurious and distortion design DAC Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF RF 0/90 PHASE JESD204B OUTPUT LPF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at SHIFTER SYNCOUTx 180 MHz IF SFDR = 72 dBc at 180 MHz IF, 6 dBFS single tone DAC SYSREF Flexible 8-lane JESD204B interface Multiple chip synchronization QUAD DAC Fixed latency LO IN MOD SPI Data generator latency compensation QUAD MOD ADRF6720-27 Input signal power detection DAC High performance, low noise phase-locked loop (PLL) clock multiplier RF 0/90 PHASE JESD204B Digital inverse sinc filter LPF OUTPUT 1 SHIFTER Digital quadrature modulation using a numerically SYNCOUTx controlled oscillator (NCO) DAC Nyquist band selectionmix mode Selectable 1, 2, 4, and 8 interpolation filters AD9154 Low power: 2.11 W at 1.6 GSPS, full operating conditions LO IN MOD SPI 88-lead, exposed pad LFCSP DAC DAC CLOCK SPI APPLICATIONS Figure 1. Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radio Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment GENERAL DESCRIPTION The AD9154 is a quad, 16-bit, high dynamic range digital-to- The full-scale output current can be programmed over a range analog converter (DAC) that provides a maximum sample rate of 4 mA to 20 mA. The AD9154 is available in two different of 2.4 GSPS, permitting multicarrier generation up to the Nyquist 88-lead LFCSP packages. frequency in baseband mode. The AD9154 includes features PRODUCT HIGHLIGHTS optimized for direct conversion transmit applications, including 1. Ultrawide signal bandwidth enables emerging wideband complex digital modulation, input signal power detection, and and multiband wireless applications. gain, phase, and offset compensation. The DAC outputs are 2. Advanced low spurious and distortion design techniques optimized to interface seamlessly with the ADRF6720-27 radio provide high quality synthesis of wideband signals from frequency quadrature modulator (AQM) from Analog Devices, baseband to high intermediate frequencies. Inc. In mix mode, the AD9154 DAC can reconstruct carriers in 3. JESD204B Subclass 1 support simplifies multichip the second and third Nyquist zones. A serial port interface (SPI) synchronization. provides the programming/readback of internal parameters. 4. Small package size with a 12 mm 12 mm footprint. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11389-101AD9154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Link Latency Setup ..................................................................... 30 Applications ....................................................................................... 1 Crossbar Setup ............................................................................ 32 Functional Block Diagram .............................................................. 1 JESD204B Serial Data Interface .................................................... 33 General Description ......................................................................... 1 JESD204B Overview .................................................................. 33 Product Highlights ........................................................................... 1 Physical Layer ............................................................................. 34 Revision History ............................................................................... 3 Data Link Layer .......................................................................... 37 Detailed Functional Block Diagram .............................................. 4 Transport Layer .......................................................................... 45 Specifications ..................................................................................... 5 JESD204B Test Modes ............................................................... 58 DC Specifications ......................................................................... 5 JESD204B Error Monitoring..................................................... 59 Digital Specifications ................................................................... 6 Digital Datapath ............................................................................. 62 Maximum DAC Update Rate Speed Specifications by Supply .... 7 Dual Paging ................................................................................. 62 JESD204B Serial Interface Speed Specifications ...................... 7 Data Format ................................................................................ 62 SYSREF to DAC Clock Timing Specifications ......................... 8 Interpolation Modes .................................................................. 62 Digital Input Data Timing Specifications ................................. 8 Digital Modulation ..................................................................... 63 Latency Variation Specifications ................................................ 9 Inverse Sinc ................................................................................. 64 JESD204B Interface Electrical Specifications ........................... 9 Digital Gain, Phase Adjust, DC Offset, and Group Delay .... 64 AC Specifications ........................................................................ 10 I to Q Swap .................................................................................. 65 Absolute Maximum Ratings .......................................................... 11 NCO Alignment ......................................................................... 65 Thermal Resistance .................................................................... 11 Downstream Protection ............................................................ 66 ESD Caution ................................................................................ 11 Datapath PRBS ........................................................................... 68 Pin Configuration and Function Descriptions ........................... 12 DC Test Mode ............................................................................. 69 Typical Performance Characteristics ........................................... 14 Interrupt Request Operation ........................................................ 70 Terminology .................................................................................... 20 Interrupt Service Routine .......................................................... 70 Theory of Operation ...................................................................... 21 DAC Input Clock Configurations ................................................ 72 Serial Port Operation ..................................................................... 22 Driving the CLK Inputs .......................................................... 72 Data Format ................................................................................ 22 DAC PLL Fixed Register Writes ............................................... 72 Serial Port Pin Descriptions ...................................................... 22 Condition Specific Register Writes .......................................... 72 Serial Port Options ..................................................................... 22 Starting the PLL .......................................................................... 73 Chip Information ............................................................................ 24 Analog Outputs............................................................................... 75 Device Setup Guide ........................................................................ 25 Transmit DAC Operation .......................................................... 75 Step 1: Start Up the DAC ........................................................... 25 Normal and Mix Modes of Operation ..................................... 76 Step 2: Digital Datapath ............................................................. 26 Temperature Sensor ....................................................................... 77 Step 3: Transport Layer .............................................................. 26 Example Start-Up Sequence .......................................................... 78 Step 4: Physical Layer ................................................................. 27 Step 1: Start Up the DAC ........................................................... 78 Step 5: Data Link Layer .............................................................. 28 Step 2: Digital Datapath ............................................................. 78 Step 6: Error Monitoring ........................................................... 28 Step 3: Transport Layer .............................................................. 79 DAC PLL Setup ............................................................................ 28 Step 4: Physical Layer ................................................................. 79 Interpolation ............................................................................... 29 Step 5: Data Link Layer .............................................................. 80 JESD204B Setup .......................................................................... 29 Step 6: Error Monitoring ........................................................... 80 Equalization Mode Setup .......................................................... 30 Board Level Hardware Considerations ........................................ 81 Rev. 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