11-Bit/16-Bit, 12 GSPS, RF Digital-to-Analog Converters Data Sheet AD9161/AD9162 In baseband mode, wide bandwidth capability combines with FEATURES high dynamic range to support DOCSIS 3.1 cable infrastructure DAC update rate up to 12 GSPS (minimum) compliance from the minimum of two carriers to full maximum Direct RF synthesis at 6 GSPS (minimum) spectrum of 1.794 GHz. A 2 interpolator filter (FIR85) enables DC to 2.5 GHz in baseband 1 bypass mode the AD9161/AD9162 to be configured for lower data rates and DC to 6 GHz in 2 nonreturn-to-zero (NRZ) mode converter clocking to reduce the overall system power and ease 1.5 GHz to 7.5 GHz in Mix-Mode the filtering requirements. In Mix-Mode operation, the AD9161/ Bypassable interpolation (1 or bypass mode) AD9162 can reconstruct RF carriers in the second and third 2, 3, 4, 6, 8, 12, 16, 24 Nyquist zones up to 7.5 GHz while still maintaining exceptional Excellent dynamic performance dynamic range. The output current can be programmed from APPLICATIONS 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes Broadband communications systems that are programmable in terms of lane speed and number of DOCSIS 3.1 cable modem termination system (CMTS)/ lanes to enable application flexibility. video on demand (VOD)/edge quadrature amplitude modulation (EQAM) A serial peripheral interface (SPI) can configure the AD9161/ Wireless communications infrastructure AD9162 and monitor the status of all registers. The AD9161/ W-CDMA, LTE, LTE-A, point to point AD9162 are offered in an 165-ball, 8.0 mm 8.0 mm, 0.5 mm Instrumentation, automatic test equipment (ATE) pitch, CSP BGA package and in an 169-ball, 11 mm 11 mm, Radars and jammers 0.8 mm pitch, CSP BGA package, including a leaded ball option for the AD9162. GENERAL DESCRIPTION 1 The AD9161/AD9162 are high performance, 11-bit/16-bit PRODUCT HIGHLIGHTS digital-to-analog converters (DACs) that supports data rates to 1. High dynamic range and signal reconstruction bandwidth 6 GSPS. The DAC core is based on a quad-switch architecture supports RF signal synthesis of up to 7.5 GHz. coupled with a 2 interpolator filter that enables an effective 2. Up to eight lanes JESD204B SERDES interface flexible in DAC update rate of up to 12 GSPS in some modes. The high terms of number of lanes and lane speed. dynamic range and bandwidth makes these DACs ideally suited 3. Bandwidth and dynamic range to meet DOCSIS 3.1 for the most demanding high speed radio frequency (RF) DAC compliance with margin. applications. FUNCTIONAL BLOCK DIAGRAM RESET IRQ ISET VREF SDIO SDO VREF SPI AD9161/AD9162 CS SCLK NRZ RZ MIX SERDIN0 HB INV NCO SERDIN7 2 SINC JESD DAC OUTPUT SYNCOUT CORE SYSREF HB 2 CLOCK HB TO JESD DISTRIBUTION HB 2, TO DATAPATH 3 4, 8 TX ENABLE CLK Figure 1. 1 Protected by U.S. Patents 6,842,132 and 7,796,971. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DATA LATCH 14379-001AD9161/AD9162 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Overview .................................................................. 46 Applications ....................................................................................... 1 Physical Layer ............................................................................. 47 General Description ......................................................................... 1 Data Link Layer .......................................................................... 50 Product Highlights ........................................................................... 1 Transport Layer .......................................................................... 58 Functional Block Diagram .............................................................. 1 JESD204B Test Modes ............................................................... 60 Revision History ............................................................................... 3 JESD204B Error Monitoring ..................................................... 62 Specifications ..................................................................................... 4 Hardware Considerations ......................................................... 64 DC Specifications ......................................................................... 4 Main Digital Datapath ................................................................... 65 DAC Input Clock Overclocking Specifications ........................ 5 Data Format ................................................................................ 65 Power Supply DC Specifications ................................................ 5 Interpolation Filters ................................................................... 65 Serial Port and CMOS Pin Specifications ................................. 8 Digital Modulation ..................................................................... 68 JESD204B Serial Interface Speed Specifications ...................... 9 Inverse Sinc ................................................................................. 70 SYSREF to DAC Clock Timing Specifications ....................... 9 Downstream Protection ............................................................ 70 Digital Input Data Timing Specifications ............................... 10 Datapath PRBS ........................................................................... 71 JESD204B Interface Electrical Specifications ......................... 10 Datapath PRBS IRQ ................................................................... 71 AC Specifications ........................................................................ 11 Interrupt Request Operation ........................................................ 73 Absolute Maximum Ratings .......................................................... 13 Interrupt Service Routine .......................................................... 73 Reflow Profile .............................................................................. 13 Applications Information .............................................................. 74 Thermal Management ............................................................... 13 Hardware Considerations ......................................................... 74 Thermal Resistance .................................................................... 13 Analog Interface Considerations .................................................. 77 ESD Caution ................................................................................ 13 Analog Modes of Operation ..................................................... 77 Pin Configurations and Function Descriptions ......................... 14 Clock Input .................................................................................. 78 Typical Performance Characteristics ........................................... 18 Shuffle Mode ............................................................................... 79 AD9161 ........................................................................................ 18 DLL ............................................................................................... 79 AD9162 ........................................................................................ 28 Voltage Reference ....................................................................... 79 Terminology .................................................................................... 42 Temperature Sensor ................................................................... 80 Theory of Operation ...................................................................... 43 Analog Outputs .......................................................................... 80 Serial Port Operation ..................................................................... 44 Start-Up Sequence .......................................................................... 82 Data Format ................................................................................ 44 Register Summary .......................................................................... 84 Serial Port Pin Descriptions ...................................................... 44 Register Details ............................................................................... 91 Serial Port Options ..................................................................... 44 Outline Dimensions ..................................................................... 143 JESD204B Serial Data Interface .................................................... 46 Ordering Guide ........................................................................ 144 Rev. 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