16-Bit, 12 GSPS, RF DAC and Digital Upconverter Data Sheet AD9163 The wide bandwidth of up to 1 GHz and the complex NCO and FEATURES digital upconverter enable dual band and triple band direct RF DAC update rate up to 12 GSPS (minimum) synthesis of wireless infrastructure signals, eliminating costly Direct RF synthesis at 6 GSPS (minimum) analog upconverters. DC to 3 GHz in nonreturn-to-zero (NRZ) mode DC to 6 GHz in 2 NRZ mode Wide analog bandwidth capability combines with high dynamic 1.5 GHz to 7.5 GHz in Mix-Mode range to support DOCSIS 3.1 cable infrastructure compliance Selectable interpolation from the minimum of one carrier up to 1 GHz of signal bandwidth, 6, 8, 12, 16, 24 making it ideal for cable multiple dwelling unit (MDU) applications. Excellent dynamic performance A 2 interpolator filter (FIR85) enables the AD9163 to be config- ured for lower data rates and converter clocking to reduce the APPLICATIONS overall system power and ease the filtering requirements. In Broadband communications systems Mix-Mode operation, the AD9163 can reconstruct RF carriers DOCSIS 3.1 cable modem termination system (CMTS)/ in the second and third Nyquist zones up to 7.5 GHz while still video on demand (VOD)/edge quadrature amplitude maintaining exceptional dynamic range. The output current can modulation (EQAM) be programmed from 8 mA to 38.76 mA. The AD9163 data Wireless communications infrastructure interface consists of up to eight JESD204B serializer/deserializer MC-GSM, W-CDMA, LTE, LTE-A, point to point (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility. GENERAL DESCRIPTION 1 A serial peripheral interface (SPI) configures the AD9163 and The AD9163 is a high performance, 16-bit digital-to-analog monitors the status of all the registers. The AD9163 is offered in converter (DAC) that supports data rates to 6 GSPS. The DAC a 169-ball, 11 mm 11 mm, 0.8 mm pitch CSP BGA package. core is based on a quad-switch architecture coupled with a 2 interpolator filter that enables an effective DAC update rate of PRODUCT HIGHLIGHTS up to 12 GSPS in some modes. The high dynamic range and 1. High dynamic range and signal reconstruction bandwidth bandwidth makes this DAC ideally suited for the most demanding supports RF signal synthesis of up to 7.5 GHz. high speed radio frequency (RF) DAC applications. 2. Up to eight lanes JESD204B SERDES interface, flexible in Superior RF performance and deep interpolation rates enable terms of number of lanes and lane speed. use of the AD9163 in many wireless infrastructure applications, 3. Bandwidth and dynamic range to meet multiband wireless including MC-GSM, W-CDMA, LTE, and LTE-A. communications standards with margin. FUNCTIONAL BLOCK DIAGRAM RESET IRQ ISET VREF SDIO SDO VREF SPI AD9163 CS SCLK NRZ RZ MIX SERDIN0 HB INV NCO SERDIN7 JESD 2 SINC DAC OUTPUT SYNCOUT CORE SYSREF HB 2 CLOCK HB TO JESD DISTRIBUTION HB 2, TO DATAPATH 3 4, 8 TX ENABLE CLK Figure 1. 1 Protected by U.S. Patents 6,842,132 and 7,796,971. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DATA LATCH 14415-001AD9163 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Serial Data Interface .................................................... 31 Applications ....................................................................................... 1 JESD204B Overview .................................................................. 31 General Description ......................................................................... 1 Physical Layer ............................................................................. 32 Product Highlights ........................................................................... 1 Data Link Layer .......................................................................... 35 Functional Block Diagram .............................................................. 1 Transport Layer .......................................................................... 43 Revision History ............................................................................... 3 JESD204B Test Modes ............................................................... 45 Specifications ..................................................................................... 4 JESD204B Error Monitoring ..................................................... 47 DC Specifications ......................................................................... 4 Hardware Considerations ......................................................... 49 DAC Input Clock Overclocking Specifications ........................ 5 Main Digital Datapath ................................................................... 50 Power Supply DC Specifications ................................................ 5 Data Format ................................................................................ 50 Serial Port and CMOS Pin Specifications ................................. 6 Interpolation Filters ................................................................... 50 JESD204B Serial Interface Speed Specifications ...................... 7 Digital Modulation ..................................................................... 53 SYSREF to DAC Clock Timing Specifications ....................... 7 Inverse Sinc ................................................................................. 55 Digital Input Data Timing Specifications ................................. 8 Downstream Protection ............................................................ 55 JESD204B Interface Electrical Specifications ........................... 8 Datapath PRBS ........................................................................... 56 AC Specifications .......................................................................... 9 Datapath PRBS IRQ ................................................................... 56 Absolute Maximum Ratings .......................................................... 10 Interrupt Request Operation ........................................................ 58 Reflow Profile .............................................................................. 10 Interrupt Service Routine .......................................................... 58 Thermal Management ............................................................... 10 Applications Information .............................................................. 59 Thermal Resistance .................................................................... 10 Hardware Considerations ......................................................... 59 ESD Caution ................................................................................ 10 Analog Interface Considerations .................................................. 62 Pin Configuration and Function Descriptions ........................... 11 Analog Modes of Operation ..................................................... 62 Typical Performance Characteristics ........................................... 13 Clock Input .................................................................................. 63 Static Linearity ............................................................................ 13 Shuffle Mode ............................................................................... 64 AC Performance (NRZ Mode) ................................................. 14 DLL ............................................................................................... 64 AC (Mix-Mode) .......................................................................... 19 Voltage Reference ....................................................................... 64 DOCSIS Performance (NRZ Mode) ........................................ 22 Temperature Sensor ................................................................... 65 Terminology .................................................................................... 27 Analog Outputs .......................................................................... 65 Theory of Operation ...................................................................... 28 Start-Up Sequence .......................................................................... 67 Serial Port Operation ..................................................................... 29 Register Summary .......................................................................... 69 Serial Data Format ..................................................................... 29 Register Details ............................................................................... 76 Serial Port Pin Descriptions ...................................................... 29 Outline Dimensions ..................................................................... 126 Serial Port Options ..................................................................... 29 Ordering Guide ........................................................................ 126 Rev. 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