16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer Data Sheet AD9164 When combined with a 100 MHz serial peripheral interface (SPI) FEATURES and fast hop modes, phase coherent fast frequency hopping (FFH) DAC update rate up to 12 GSPS (minimum) is enabled, with several modes to support multiple applications. Direct RF synthesis at 6 GSPS (minimum) DC to 2.5 GHz in baseband mode In baseband mode, wide analog bandwidth capability combines DC to 6 GHz in 2 nonreturn-to-zero (NRZ) mode with high dynamic range to support DOCSIS 3.1 cable infrastruc- 1.5 GHz to 7.5 GHz in Mix-Mode ture compliance from the minimum of one carrier up to the full Bypassable interpolation maximum spectrum of 1.791 GHz of signal bandwidth. A 2 2, 3, 4, 6, 8, 12, 16, 24 interpolator filter (FIR85) enables the AD9164 to be configured Excellent dynamic performance for lower data rates and converter clocking to reduce the overall Fast frequency hopping system power and ease the filtering requirements. In Mix-Mode operation, the AD9164 can reconstruct RF carriers in the second APPLICATIONS and third Nyquist zones up to 7.5 GHz while still maintaining Broadband communications systems exceptional dynamic range. The output current can be programmed DOCSIS 3.1 CMTS/ video on demand (VOD)/edge from 8 mA to 38.76 mA. The AD9164 data interface consists of quadrature amplitude modulation (EQAM) up to eight JESD204B serializer/deserializer (SERDES) lanes Wireless communications infrastructure that are programmable in terms of lane speed and number of W-CDMA, LTE, LTE-A, point to point lanes to enable application flexibility. GENERAL DESCRIPTION An SPI interface configures the AD9164 and monitors the status of 1 all registers. The AD9164 is offered in a 165-ball, 8 mm 8 mm, The AD9164 is a high performance, 16-bit digital-to-analog 0.5 mm pitch CSP BGA package, and a 169-ball, 11 mm 11 mm, converter (DAC) and direct digital synthesizer (DDS) that 0.8 mm pitch, CSP BGA package, including a leaded ball option. supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2 interpolator filter PRODUCT HIGHLIGHTS that enables an effective DAC update rate of up to 12 GSPS in 1. High dynamic range and signal reconstruction bandwidth some modes. The high dynamic range and bandwidth makes supports RF signal synthesis of up to 7.5 GHz. these DACs ideally suited for the most demanding high speed 2. Up to eight lanes JESD204B SERDES interface flexible in radio frequency (RF) DAC applications. terms of number of lanes and lane speed. The DDS consists of a bank of 32, 32-bit numerically controlled 3. Bandwidth and dynamic range to meet DOCSIS 3.1 oscillators (NCOs), each with its own phase accumulator. compliance and multiband wireless communications standards with margin. FUNCTIONAL BLOCK DIAGRAM RESET IRQ ISET VREF SDIO SDO VREF SPI AD9164 CS SCLK NRZ RZ MIX SERDIN0 HB INV NCO SERDIN7 JESD 2 SINC DAC OUTPUT SYNCOUT CORE SYSREF HB 2 HB TO JESD CLOCK 2, DISTRIBUTION HB TO DATAPATH 4, 3 8 TX ENABLE CLK Figure 1. 1 Protected by U.S. Patents 6,842,132 and 7,796,971. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DATA LATCH 14414-001AD9164 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Overview .................................................................. 34 Applications ....................................................................................... 1 Physical Layer ............................................................................. 35 General Description ......................................................................... 1 Data Link Layer .......................................................................... 38 Product Highlights ........................................................................... 1 Transport Layer .......................................................................... 46 Functional Block Diagram .............................................................. 1 JESD204B Test Modes ............................................................... 48 Revision History ............................................................................... 3 JESD204B Error Monitoring ..................................................... 50 Specifications ..................................................................................... 4 Hardware Considerations ......................................................... 52 DC Specifications ......................................................................... 4 Main Digital Datapath ................................................................... 53 DAC Input Clock Overclocking Specifications ........................ 5 Data Format ................................................................................ 53 Power Supply DC Specifications ................................................ 5 Interpolation Filters ................................................................... 53 Serial Port and CMOS Pin Specifications ................................. 7 Digital Modulation ..................................................................... 56 JESD204B Serial Interface Speed Specifications ...................... 8 Inverse Sinc ................................................................................. 58 SYSREF to DAC Clock Timing Specifications ....................... 8 Downstream Protection ............................................................ 59 Digital Input Data Timing Specifications ................................. 9 Datapath PRBS ........................................................................... 59 JESD204B Interface Electrical Specifications ........................... 9 Datapath PRBS IRQ ................................................................... 60 AC Specifications ........................................................................ 10 Interrupt Request Operation ........................................................ 61 Absolute Maximum Ratings .......................................................... 11 Interrupt Service Routine .......................................................... 61 Reflow Profile .............................................................................. 11 Applications Information .............................................................. 62 Thermal Management ............................................................... 11 Hardware Considerations ......................................................... 62 Thermal Resistance .................................................................... 11 Analog Interface Considerations .................................................. 65 ESD Caution ................................................................................ 11 Analog Modes of Operation ..................................................... 65 Pin Configurations and Function Descriptions ......................... 12 Clock Input .................................................................................. 66 Typical Performance Characteristics ........................................... 16 Shuffle Mode ............................................................................... 67 Static Linearity ............................................................................ 16 DLL ............................................................................................... 67 AC Performance (NRZ Mode) ................................................. 17 Voltage Reference ....................................................................... 67 AC (Mix-Mode) .......................................................................... 22 Temperature Sensor ................................................................... 67 DOCSIS Performance (NRZ Mode) ........................................ 25 Analog Outputs .......................................................................... 68 Terminology .................................................................................... 30 Start-Up Sequence .......................................................................... 71 Theory of Operation ...................................................................... 31 Register Summary .......................................................................... 73 Serial Port Operation ..................................................................... 32 Register Details ............................................................................... 82 Serial Data Format ..................................................................... 32 Outline Dimensions ..................................................................... 136 Serial Port Pin Descriptions ...................................................... 32 Ordering Guide ........................................................................ 137 Serial Port Options ..................................................................... 32 JESD204B Serial Data Interface .................................................... 34 Rev. D Page 2 of 137