Dual, 16-Bit, 6.2 GSPS RF DAC with Single Channelizer Data Sheet AD9171 FEATURES GENERAL DESCRIPTION Supports single-band wireless applications The AD9171 is a high performance, dual, 16-bit digital-to-analog 1 complex data input channel per RF DAC converter (DAC) that supports DAC sample rates to 6.2 GSPS. 516 MSPS maximum complex input data rate per input The device features an 8-lane, 15.4 Gbps JESD204B data input port, channel a high performance, on-chip DAC clock multiplier, and digital 1 independent NCO per input channel signal processing capabilities targeted at single-band direct to Proprietary, low spurious and distortion design radio frequency (RF) wireless applications. 2-tone IMD = 83 dBc at 1.8 GHz, 7 dBFS/tone RF output The AD9171 features one complex data input channels per RF SFDR < 80 dBc at 1.8 GHz, 7 dBFS RF output DAC. Each data input channel includes a configurable gain Flexible 8-lane, 15.4 Gbps JESD204B interface stage, an interpolation filter, and a channel numerically Supports single-band use cases controlled oscillator (NCO) for flexible, frequency planning. The Supports 12-bit high density mode for increased data device supports up to a 516 MSPS complex data rate per input throughput channel. Multiple chip synchronization The AD9171 is available in a 144-ball BGA ED package. Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input PRODUCT HIGHLIGHTS data rates 1. Supports one complex data input channel per RF DAC at a 2, 3, 4, and 6 configurable data channel interpolation maximum complex input data rate of 513 MSPS with 12-bit 6 and 8 configurable final interpolation resolution and 516 MSPS with 16-bit resolution options. Final 48-bit NCO that operates at the DAC rate to support There is one independent NCO per input channel. frequency synthesis up to 3.1 GHz 2. Low power dual converter decreases the amount of power Transmit enable function allows extra power saving and consumption needed in high bandwidth and multichannel downstream circuitry protection applications. High performance, low noise PLL clock multiplier Supports 6.2 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 1.45 W at 6 GSPS, single-channel mode 10 mm 10 mm, 144-ball BGA ED with metal enhanced thermal lid, 0.80 mm pitch APPLICATIONS Wireless communications infrastructure Single-band base station radios Instrumentation, automatic test equipment (ATE) Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9171 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Serial Data Interface .................................................... 23 Applications ....................................................................................... 1 JESD204B Overview .................................................................. 23 General Description ......................................................................... 1 Physical Layer ............................................................................. 25 Product Highlights ........................................................................... 1 Data Link Layer .......................................................................... 27 Revision History ............................................................................... 2 Syncing LMFC Signals ............................................................... 30 Functional Block Diagram .............................................................. 3 Transport Layer .......................................................................... 35 Specif icat ions ..................................................................................... 4 JESD204B Test Modes ............................................................... 36 DC Specifications ......................................................................... 4 JESD204B Error Monitoring ..................................................... 38 Digital Specifications ................................................................... 5 Digital Datapath ............................................................................. 41 Power Supply DC Specifications ................................................ 5 Total Datapath Interpolation .................................................... 41 Serial Port and CMOS Pin Specifications ................................. 6 Channel Digital Datapath ......................................................... 42 Digital Input Data Timing Specifications ................................. 7 Main Digital Datapath ............................................................... 45 JESD204B Interface Electrical and Speed Specifications ........ 8 Interrupt Request Operation ........................................................ 51 Input Data Rates and Signal Bandwidth Specifications .......... 8 Interrupt Service Routine .......................................................... 51 AC Specifications .......................................................................... 9 Applications Information .............................................................. 52 Absolute Maximum Ratings .......................................................... 11 Hardware Considerations ......................................................... 52 Reflow Profile .............................................................................. 11 Analog Interface Considerations .................................................. 55 Thermal Characteristics ............................................................ 11 DAC Input Clock Configurations ............................................ 55 ESD Caution ................................................................................ 11 Clock Output Driver .................................................................. 57 Pin Configuration and Function Descriptions ........................... 12 Analog Outputs .......................................................................... 57 Typical Performance Characteristics ........................................... 15 Start-Up Sequence .......................................................................... 58 Terminology .................................................................................... 19 Register Summary .......................................................................... 65 Theory of Operation ...................................................................... 20 Register Details ............................................................................... 73 Serial Port Operation ..................................................................... 21 Outline Dimensions ..................................................................... 134 Data Format ................................................................................ 21 Ordering Guide ........................................................................ 134 Serial Port Pin Descriptions ...................................................... 21 Serial Port Options ..................................................................... 21 REVISION HISTORY 8/2019Rev. A to Rev. B Changes to L12 Pin Description, Table 11 .................................. 14 Changes to Figure 12 ...................................................................... 16 Changes to SYSREF Sampling Section ...................................... 29 Added Figure 13 Renumbered Sequentially .............................. 16 Changes to Subclass 1 Section ...................................................... 30 Changes to Figure 48 and Table 32 ............................................... 43 Change to Figure 37 ....................................................................... 31 Changes to Figure 49 ...................................................................... 44 Changes to Table 32 ....................................................................... 42 Change to Table 38 ......................................................................... 47 Change to SPI CHIPGRADE Register, Table 54 ....................... 64 Changes to Figure 54 ...................................................................... 48 Change to DATAPATH NCO SYNC CFG Register, Changes to Figure 65 ...................................................................... 55 Table 54 ............................................................................................ 97 Changes to Table 49 ........................................................................ 60 Change to SPI CHIPGRADE Register, Table 55 ....................... 72 Changes to Table 50 ........................................................................ 61 Change to DATAPATH NCO SYNC CFG Register, Changes to Table 55 ........................................................................ 84 Table 54 ............................................................................................ 92 Changes to Ordering Guide ........................................................ 132 5/2019Rev. 0 to Rev. A Changes to Noise Spectral Density Parameters, Table 8 ............. 9 1/2018Revision 0: Initial Version Rev. B Page 2 of 134