Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Data Sheet AD9173 FEATURES GENERAL DESCRIPTION Supports multiband wireless applications The AD9173 is a high performance, dual, 16-bit digital-to-analog 3 bypassable, complex data input channels per RF DAC converter (DAC) that supports DAC sample rates to 12.6 GSPS. 1.54 GSPS maximum complex input data rate per input The device features an 8-lane, 15.4 Gbps JESD204B data input port, channel a high performance, on-chip DAC clock multiplier, and digital 1 independent NCO per input channel signal processing capabilities targeted at single-band and multiband Proprietary, low spurious and distortion design direct to radio frequency (RF) wireless applications. 2-tone IMD = 83 dBc at 1.8 GHz, 7 dBFS/tone RF output The AD9173 features three complex data input channels per RF SFDR < 80 dBc at 1.8 GHz, 7 dBFS RF output DAC that are bypassable. Each data input channel includes a Flexible 8-lane, 15.4 Gbps JESD204B interface configurable gain stage, an interpolation filter, and a channel Supports single-band and multiband use cases numerically controlled oscillator (NCO) for flexible, multiband Supports 12-bit high density mode for increased data frequency planning. The device supports up to a 1.54 GSPS throughput complex data rate per input channel and is capable of aggregating Multiple chip synchronization multiple complex input data streams up to a maximum complex Supports JESD204B Subclass 1 data rate of 1.54 GSPS. Additionally, the AD9173 supports Selectable interpolation filter for a complete set of input ultrawide bandwidth modes bypassing the channelizers to data rates provide maximum data rates of up to 3.08 GSPS (with 11-bit 1, 2, 3, 4, 6, and 8 configurable data channel resolution using 16-bit serializer/deserializer (SERDES) interpolation packing) and 3.4 GSPS (with 11-bit resolution using 12-bit 1, 2, 4, 6, 8, and 12 configurable final interpolation SERDES packing). Final 48-bit NCO that operates at the DAC rate to support The AD9173 is available in a 144-ball BGA ED package. frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and PRODUCT HIGHLIGHTS downstream circuitry protection 1. Supports single-band and multiband wireless applications High performance, low noise PLL clock multiplier with three bypassable complex data input channels per RF Supports 12.6 GSPS DAC update rate DAC at a maximum complex input data rate of 1.54 GSPS Observation ADC clock driver with selectable divide ratios with 11-bit resolution and 1.23 GSPS with 16-bit Low power resolution. One independent NCO per input channel. 2.55 W at 12 GSPS, dual channel mode 2. Ultrawide bandwidth channel bypass modes supporting up 10 mm 10 mm, 144-ball BGA ED with metal enhanced to 3.08 GSPS data rates with 11-bit resolution, 16-bit thermal lid, 0.80 mm pitch SERDES packing and 3.4 GSPS with 11-bit resolution, 12- APPLICATIONS bit SERDES packing. 3. Low power dual converter decreases the amount of power Wireless communications infrastructure consumption needed in high bandwidth and multichannel Multiband base station radios applications. Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9173 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Port Options ..................................................................... 27 Applications ....................................................................................... 1 JESD204B Serial Data Interface .................................................... 29 General Description ......................................................................... 1 JESD204B Overview .................................................................. 29 Product Highlights ........................................................................... 1 Physical Layer ............................................................................. 32 Revision History ............................................................................... 2 Data Link Layer .......................................................................... 34 Functional Block Diagram .............................................................. 3 Syncing LMFC Signals ............................................................... 37 Specif icat ions ..................................................................................... 4 Transport Layer .......................................................................... 42 DC Specifications ......................................................................... 4 JESD204B Test Modes ............................................................... 43 Digital Specifications ................................................................... 5 JESD204B Error Monitoring ..................................................... 45 Maximum DAC Sampling Rate Specifications ......................... 5 Digital Datapath ............................................................................. 48 Power Supply DC Specifications ................................................ 6 Total Datapath Interpolation .................................................... 48 Serial Port and CMOS Pin Specifications ................................. 8 Channel Digital Datapath ......................................................... 50 Digital Input Data Timing Specifications ................................. 9 Main Digital Datapath ............................................................... 53 JESD204B Interface Electrical and Speed Specifications ...... 10 Interrupt Request Operation ........................................................ 59 Input Data Rates and Signal Bandwidth Specifications ........ 10 Interrupt Service Routine .......................................................... 59 AC Specifications ........................................................................ 11 Applications Information .............................................................. 60 Absolute Maximum Ratings .......................................................... 13 Hardware Considerations ......................................................... 60 Reflow Profile .............................................................................. 13 Analog Interface Considerations .................................................. 63 Thermal Characteristics ............................................................ 13 DAC Input Clock Configurations ............................................ 63 ESD Caution ................................................................................ 13 Clock Output Driver .................................................................. 65 Pin Configuration and Function Descriptions ........................... 14 Analog Outputs .......................................................................... 65 Typical Performance Characteristics ........................................... 17 Start-Up Sequence .......................................................................... 66 Terminology .................................................................................... 24 Register Summary .......................................................................... 73 Theory of Operation ...................................................................... 25 Register Details ............................................................................... 81 Serial Port Operation ..................................................................... 27 Outline Dimensions ..................................................................... 142 Data Format ................................................................................ 27 Ordering Guide ........................................................................ 142 Serial Port Pin Descriptions ...................................................... 27 REVISION HISTORY Change to L12 Pin Description, Table 12 .................................... 16 8/2019Rev. A to Rev. B Changes to Table 17 ....................................................................... 30 Change to Figure 2 ......................................................................... 14 Change to Mode 9 Parameter, Table 18 ....................................... 31 Changes to Figure 33 ...................................................................... 22 Changes to SYSREF Sampling Section ...................................... 37 Added Figure 34 Renumbered Sequentially .............................. 22 Changes to Subclass 1 Section ...................................................... 38 Changes to Table 37 ........................................................................ 51 Changes to Figure 71 and Table 37 .............................................. 51 Changes to Figure 73 ...................................................................... 52 Change to SPI CHIPGRADE Register, Table 59 ....................... 73 Change to TB1 Parameter, Table 43 ............................................. 55 Change to DATAPATH NCO SYNC CFG Register, Change to Figure 78 ....................................................................... 56 Table 59 ............................................................................................ 76 Changes to Figure 89 ...................................................................... 63 Change to SPI CHIPGRADE Register, Table 60 ....................... 81 Changes to Table 54 ........................................................................ 68 Change to DATAPATH NCO SYNC CFG Register, Changes to Table 55 ........................................................................ 69 Table 60 .......................................................................................... 101 Changes to Table 60 ........................................................................ 81 Changes to Ordering Guide ........................................................ 142 4/2019Rev. 0 to Rev. A 11/2017Revision 0: Initial Version Changes to Noise Spectral Density (NSD) Parameters, Table 9 ... 12 Rev. B Page 2 of 142