Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Data Sheet AD9174 The AD9174 features three complex data input channels per RF FEATURES DAC datapath. Each input channel is fully bypassable. Each data Supports multiband wireless applications input channel (or channelizer) includes a configurable gain 3 bypassable, complex data input channels per RF DAC stage, an interpolation filter, and a channel numerically controlled 3.08 GSPS maximum complex input data rate per input oscillator (NCO) for flexible, multiband frequency planning. channel The AD9174 supports an input data rate of up to a 3.08 GSPS 1 independent NCO per input channel complex (inphase/quadrature (I/Q)), or up to 6.16 GSPS non- Proprietary, low spurious and distortion design complex (real), and is capable of allocating multiple complex input 2-tone IMD3 = 83 dBc at 1.84 GHz, 7 dBFS/tone RF output data streams to the assigned channels for individual processing. SFDR <80 dBc at 1.84 GHz, 7 dBFS RF output Each group of three channelizers is summed into a respective Flexible 8-lane, 15.4 Gbps JESD204B interface main datapath for additional processing when needed. Each main Supports single-band and multiband use cases datapath includes an interpolation filter and one 48-bit main NCO Supports 12-bit high density mode for increased data ahead of the RF DAC core. Using the modulator switch, the outputs throughput of a main datapath can be either routed to DAC0 alone for Multiple chip synchronization operating as a single DAC, or routed to both DAC0 and DAC1 Supports JESD204B Subclass 1 for operating as a dual, intermediate frequency DAC (IF DAC). Selectable interpolation filter for a complete set of input data rates The AD9174 also supports ultrawide data rate modes that allow 1, 2, 3, 4, 6, and 8 configurable data channel bypassing the channelizers and main datapaths to provide interpolation maximum data rates of up to 6.16 GSPS as a single, 16-bit DAC, 1, 2, 4, 6, 8, and 12 configurable final interpolation up to 3.08 GSPS as a dual, 16-bit DAC, or up to 4.1 GSPS as a Final 48-bit NCO that operates at the DAC rate to support dual, 12-bit DAC. frequency synthesis up to 6 GHz Additionally, the main NCO blocks in the AD9174 contain a bank Transmit enable function allows extra power saving and of 31, 32-bit NCOs, each with an independent phase accumulator. downstream circuitry protection Combined with a 80 MHz serial peripheral interface (SPI) for High performance, low noise PLL clock multiplier programming the NCOs, this bank allows a phase coherent, fast Supports 12.6 GSPS DAC update rate frequency hopping (FFH) for applications where the NCO Observation ADC clock driver with selectable divide ratios frequencies are continuously adjusted during operation. Low power The AD9174 is available in a 144-ball BGA ED package. 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm 10 mm, 144-ball BGA ED with metal enhanced PRODUCT HIGHLIGHTS thermal lid, 0.80 mm pitch 1. A low power, multichannel, dual DAC design reduces APPLICATIONS power consumption in higher bandwidth and multichannel applications, while maintaining performance. Wireless communications infrastructure 2. Supports single-band and multiband wireless applications Multiband base station radios with three bypassable complex data channels per RF DAC, Microwave/E-band backhaul systems or configurations that use the two main datapaths as two Instrumentation, automatic test equipment (ATE) wideband complex data channels when using the built in Radars and jammers modulator switch. GENERAL DESCRIPTION 3. A maximum complex data rate (per I or Q) of up to 3.08 GSPS The AD9174 is a high performance, dual, 16-bit digital-to-analog with 16-bit resolution, and up to 4.1 GSPS with 12-bit converter (DAC) that supports DAC sample rates up to 12.6 GSPS. resolution. The AD9174 can be alternatively configured as The device features an 8-lane, 15.4 Gbps JESD204B data input a dual DAC, with each DAC operating across an independent port, a high performance, on-chip DAC clock multiplier, and JESD204B link, at the previously described data rates. digital signal processing capabilities targeted at single-band and 4. Ultrawide bandwidth single-DAC modes, supporting up to multiband direct to radio frequency (RF) wireless applications. 6.16 GSPS data rates with 16-bit resolution. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD9174 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Serial Data Interface .................................................... 33 Applications ....................................................................................... 1 JESD204B Overview .................................................................. 33 General Description ......................................................................... 1 Physical Layer ............................................................................. 37 Product Highlights ........................................................................... 1 Data Link Layer .......................................................................... 39 Revision History ............................................................................... 2 Syncing LMFC Signals ............................................................... 41 Functional Block Diagram .............................................................. 4 Transport Layer .......................................................................... 47 Specif icat ions ..................................................................................... 5 JESD204B Test Modes ............................................................... 48 DC Specifications ......................................................................... 5 JESD204B Error Monitoring ..................................................... 50 Digital Specifications ................................................................... 6 Digital Datapath ............................................................................. 53 Maximum DAC Sampling Rate Specifications ......................... 6 Total Datapath Interpolation .................................................... 53 Power Supply DC Specifications ................................................ 7 Channel Digital Datapath ......................................................... 55 Serial Port and CMOS Pin Specifications ............................... 10 Main Digital Datapath ............................................................... 58 Digital Input Data Timing Specifications ............................... 11 NCO Only Mode ........................................................................ 62 JESD204B Interface Electrical and Speed Specifications ...... 12 Modulator Switch ....................................................................... 64 Input Data Rates and Signal Bandwidth Specifications ........ 13 Interrupt Request Operation ........................................................ 68 AC Specifications ........................................................................ 14 Interrupt Service Routine .......................................................... 68 Absolute Maximum Ratings .......................................................... 16 Analog Interface ............................................................................. 69 Reflow Profile .............................................................................. 16 DAC Input Clock Configurations ............................................ 69 Thermal Characteristics ............................................................ 16 Clock Output Driver .................................................................. 71 ESD Caution ................................................................................ 16 Analog Outputs .......................................................................... 71 Pin Configuration and Function Descriptions ........................... 17 Applications Information .............................................................. 73 Typical Performance Characteristics ........................................... 20 Hardware Considerations ......................................................... 73 Terminology .................................................................................... 28 Start-Up Sequence .......................................................................... 76 Theory of Operation ...................................................................... 29 Register Summary .......................................................................... 83 Serial Port Operation ..................................................................... 31 Register Details ............................................................................... 95 Data Format ................................................................................ 31 Outline Dimensions ..................................................................... 165 Serial Port Pin Descriptions ...................................................... 31 Ordering Guide ........................................................................ 165 Serial Port Options ..................................................................... 32 REVISION HISTORY 7/2019Rev. A to Rev. B Changes to Noise Spectral Density (NSD) Parameters, Changes to Digital Gain Section ................................................... 55 Table 9 .............................................................................................. 13 Changes to Table 37 ........................................................................ 56 Changes to Figure 16 Caption and Figure 17 Caption .............. 21 Changes to Table 43 ........................................................................ 60 Change to Table 17 ......................................................................... 33 Changes to NCO Only Mode Section .......................................... 62 Changes to SYSREF Sampling Section ...................................... 41 Changes to DAC Full-Scale Power Section ................................. 71 Changes to Subclass 1 Section ...................................................... 42 Changes to Table 56 ........................................................................ 79 Changes to Figure 73 and Table 37 .............................................. 55 Changes to Table 57 ........................................................................ 80 Change to Complex Modulator Switch Configurations Changes to Table 62 ...................................................................... 105 S ection .............................................................................................. 65 Changes to DAC On-Chip PL Section ........................................ 69 5/2019Rev. 0 to Rev. A Change to M DIVIDER 1 Bit Description, Table 52 ............... 75 Change to Input Data Rate Per Input Channel Parameter, Change to SPI CHIPGRADE Register, Table 61 ....................... 82 Table 8 .............................................................................................. 12 Rev. B Page 2 of 165