Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Data Sheet AD9175 multiplier, and digital signal processing capabilities targeted at FEATURES single-band and multiband direct to radio frequency (RF) Supports multiband wireless applications wireless applications. 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input The AD9175 features three complex data input channels per RF channel, 11-bit resolution DAC datapath. Each input channel is fully bypassable. Each 1 independent NCO per input channel data input channel (or channelizer) includes a configurable gain Proprietary, low spurious and distortion design stage, an interpolation filter, and a channel numerically controlled 2-tone IMD3 = 83 dBc at 1.84 GHz, 7 dBFS/tone RF output oscillator (NCO) for flexible, multiband frequency planning. The SFDR <80 dBc at 1.84 GHz, 7 dBFS RF output AD9175 supports an input data rate of up to 3.08 GSPS complex Flexible 8-lane, 15.4 Gbps JESD204B interface (in-phase/quadrature (I/Q)), or up to 3.4 GSPS noncomplex Supports single-band and multiband use cases (real), and is capable of allocating multiple complex input data Supports 12-bit high density mode for increased data streams to the assigned channels for individual processing. Each throughput group of three channelizers is summed into a respective main Multiple chip synchronization datapath for additional processing when needed. Each main Supports JESD204B Subclass 1 datapath includes an interpolation filter and one 48-bit main Selectable interpolation filter for a complete set of input NCO ahead of the RF DAC core. Using the modulator switch, data rates the outputs of a main datapath can be either routed to DAC0 1, 2, 3, 4, 6, and 8 configurable data channel alone for operating as a single DAC, or routed to both DAC0 interpolation and DAC1 for operating as a dual, intermediate frequency DAC 1, 2, 4, 6, 8, and 12 configurable final interpolation (IF DAC). Final 48-bit NCO that operates at the DAC rate to support The AD9175 also supports ultrawide data rate modes that allow frequency synthesis up to 6 GHz bypassing the channelizers and main datapaths to provide Transmit enable function allows extra power saving and maximum data rates of up to 3.4 GSPS as a dual, 11-bit DAC. downstream circuitry protection The AD9175 is available in a 144-ball BGA ED package. High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate PRODUCT HIGHLIGHTS Observation ADC clock driver with selectable divide ratios 1. A low power, multichannel, dual DAC design reduces Low power power consumption in higher bandwidth and multichannel 2.54 W with 2 DACs at 12 GSPS, DAC PLL on applications, while maintaining performance. 10 mm 10 mm, 144-ball BGA ED with metal enhanced 2. Supports single-band and multiband wireless applications thermal lid, 0.80 mm pitch with three bypassable complex data channels per RF DAC, APPLICATIONS or configurations that use the two main datapaths as two wideband complex data channels when using the built in Wireless communications infrastructure modulator switch. Multiband base station radios 3. A maximum complex data rate (per I or Q) of up to Microwave/E-band backhaul systems 3.08 GSPS with 11-bit resolution, and up to 1.23 GSPS with Instrumentation, automatic test equipment (ATE) 16-bit resolution. The AD9175 can be alternatively Radars and jammers configured as a dual DAC, with each DAC operating across GENERAL DESCRIPTION an independent JESD204B link, at the previously described The AD9175 is a high performance, dual, 16-bit digital-to- data rates. analog converter (DAC) that supports DAC sample rates up to 4. Ultrawide bandwidth single DAC modes supporting up to 12.6 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B 3.4 GSPS with 11-bit resolution, 12-bit SERDES packing. data input port, a high performance, on-chip DAC clock Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. 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AD9175 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Serial Data Interface .................................................... 31 Applications ....................................................................................... 1 JESD204B Overview .................................................................. 31 General Description ......................................................................... 1 Physical Layer ............................................................................. 35 Product Highlights ........................................................................... 1 Data Link Layer .......................................................................... 37 Revision History ............................................................................... 2 Syncing LMFC Signals ............................................................... 39 Functional Block Diagram .............................................................. 3 Transport Layer .......................................................................... 45 Specif icat ions ..................................................................................... 4 JESD204B Test Modes ............................................................... 46 DC Specifications ......................................................................... 4 JESD204B Error Monitoring ..................................................... 48 Digital Specifications ................................................................... 5 Digital Datapath ............................................................................. 51 Maximum DAC Sampling Rate Specifications ......................... 5 Total Datapath Interpolation .................................................... 51 Power Supply DC Specifications ................................................ 6 Channel Digital Datapath ......................................................... 52 Serial Port and CMOS Pin Specifications ................................. 8 Main Digital Datapath ............................................................... 55 Digital Input Data Timing Specifications ................................. 9 NCO Only Mode ........................................................................ 59 JESD204B Interface Electrical and Speed Specifications ...... 10 Modulator Switch ....................................................................... 59 Input Data Rates and Signal Bandwidth Specifications ........ 11 Interrupt Request Operation ........................................................ 63 AC Specifications ........................................................................ 12 Interrupt Service Routine .......................................................... 63 Absolute Maximum Ratings .......................................................... 14 Analog Interface ............................................................................. 64 Reflow Profile .............................................................................. 14 DAC Input Clock Configurations ............................................ 64 Thermal Characteristics ............................................................ 14 Clock Output Driver .................................................................. 66 ESD Caution ................................................................................ 14 Analog Outputs .......................................................................... 66 Pin Configuration and Function Descriptions ........................... 15 Applications Information .............................................................. 68 Typical Performance Characteristics ........................................... 18 Hardware Considerations ......................................................... 68 Terminology .................................................................................... 26 Start-Up Sequence .......................................................................... 71 Theory of Operation ...................................................................... 27 Register Summary .......................................................................... 78 Serial Port Operation ..................................................................... 29 Register Details ............................................................................... 89 Data Format ................................................................................ 29 Outline Dimensions ..................................................................... 150 Serial Port Pin Descriptions ...................................................... 29 Ordering Guide ........................................................................ 150 Serial Port Options ..................................................................... 30 REVISION HISTORY 8/2019Rev. A to Rev. B Change to Table 18 ......................................................................... 33 Changes to Digital Gain Section ................................................... 52 Changes to SYSREF Sampling Section ...................................... 40 Changes to Figure 75 and Table 37 ............................................... 53 Changes to Subclass 1 Section ...................................................... 41 Changes to Table 43 ........................................................................ 57 Change to Table 37 ......................................................................... 53 Changes to NCO Only Mode Section .......................................... 59 Change to Calibration NCO Section ........................................... 58 Changes to DAC Full-Scale Power Section ................................. 66 Change to Complex Modulator Switch Configurations Changes to Table 55 ........................................................................ 74 S ection .............................................................................................. 61 Changes to Table 56 ........................................................................ 75 Changes to DAC On-Chip PLL Section ...................................... 65 Changes to Table 61 ...................................................................... 100 Changes to Table 51 ....................................................................... 71 Changes to Table 60 ....................................................................... 78 5/2019Rev. 0 to Rev. A Changes to Table 61 ....................................................................... 89 Changes to Table 9 .......................................................................... 13 12/2018Revision 0: Initial Version Changes to Table 17 ........................................................................ 32 Rev. B Page 2 of 150