Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Data Sheet AD9176 port, a high performance, on-chip DAC clock multiplier, and FEATURES digital signal processing capabilities targeted at single-band and Supports multiband wireless applications multiband direct to radio frequency (RF) wireless applications. 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input The AD9176 features three complex data input channels per RF channel DAC datapath. Each input channel is fully bypassable. Each data 1 independent NCO per input channel input channel (or channelizer) includes a configurable gain Proprietary, low spurious and distortion design stage, an interpolation filter, and a channel numerically controlled 2-tone IMD3 = 83 dBc at 1.84 GHz, 7 dBFS/tone RF output oscillator (NCO) for flexible, multiband frequency planning. SFDR <80 dBc at 1.84 GHz, 7 dBFS RF output The AD9176 supports an input data rate of up to a 3.08 GSPS Flexible 8-lane, 15.4 Gbps JESD204B interface complex (inphase/quadrature (I/Q)), or up to 6.16 GSPS non- Supports single-band and multiband use cases complex (real), and is capable of allocating multiple complex input Supports 12-bit high density mode for increased data data streams to the assigned channels for individual processing. throughput Each group of three channelizers is summed into a respective Multiple chip synchronization main datapath for additional processing when needed. Each main Supports JESD204B Subclass 1 datapath includes an interpolation filter and one 48-bit main NCO Selectable interpolation filter for a complete set of input ahead of the RF DAC core. Using the modulator switch, the outputs data rates of a main datapath can be either routed to DAC0 alone for 1, 2, 3, 4, 6, and 8 configurable data channel operating as a single DAC, or routed to both DAC0 and DAC1 interpolation for operating as a dual, intermediate frequency DAC (IF DAC). 1, 2, 4, 6, 8, and 12 configurable final interpolation The AD9176 also supports ultrawide data rate modes that allow Final 48-bit NCO that operates at the DAC rate to support bypassing the channelizers and main datapaths to provide frequency synthesis up to 6 GHz maximum data rates of up to 6.16 GSPS as a single, 16-bit DAC, Transmit enable function allows extra power saving and up to 3.08 GSPS as a dual, 16-bit DAC, or up to 4.1 GSPS as a downstream circuitry protection dual, 12-bit DAC. High performance, low noise PLL clock multiplier The AD9176 is available in a 144-ball BGA ED package. Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios PRODUCT HIGHLIGHTS Low power 1. A low power, multichannel, dual DAC design reduces 2.54 W with 2 DACs at 12 GSPS, DAC PLL on power consumption in higher bandwidth and multichannel 10 mm 10 mm, 144-ball BGA ED with metal enhanced applications, while maintaining performance. thermal lid, 0.80 mm pitch 2. Supports single-band and multiband wireless applications APPLICATIONS with three bypassable complex data channels per RF DAC, or configurations that use the two main datapaths as two Wireless communications infrastructure wideband complex data channels when using the built in Multiband base station radios modulator switch. Microwave/E-band backhaul systems 3. A maximum complex data rate (per I or Q) of up to 3.08 GSPS Instrumentation, automatic test equipment (ATE) with 16-bit resolution, and up to 4.1 GSPS with 12-bit Radars and jammers resolution. The AD9176 can be alternatively configured as GENERAL DESCRIPTION a dual DAC, with each DAC operating across an independent The AD9176 is a high performance, dual, 16-bit digital-to-analog JESD204B link, at the previously described data rates. converter (DAC) that supports DAC sample rates up to 12.6 GSPS. 4. Ultrawide bandwidth single-DAC modes, supporting up to The device features an 8-lane, 15.4 Gbps JESD204B data input 6.16 GSPS data rates with 16-bit resolution. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. 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AD9176 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Serial Data Interface .................................................... 32 Applications ....................................................................................... 1 JESD204B Overview .................................................................. 32 General Description ......................................................................... 1 Physical Layer ............................................................................. 36 Product Highlights ........................................................................... 1 Data Link Layer .......................................................................... 38 Revision History ............................................................................... 2 Syncing LMFC Signals ............................................................... 40 Functional Block Diagram .............................................................. 3 Transport Layer .......................................................................... 46 Specif icat ions ..................................................................................... 4 JESD204B Test Modes ............................................................... 47 DC Specifications ......................................................................... 4 JESD204B Error Monitoring ..................................................... 49 Digital Specifications ................................................................... 5 Digital Datapath ............................................................................. 52 Maximum DAC Sampling Rate Specifications ......................... 5 Total Datapath Interpolation .................................................... 52 Power Supply DC Specifications ................................................ 6 Channel Digital Datapath ......................................................... 53 Serial Port and CMOS Pin Specifications ................................. 9 Main Digital Datapath ............................................................... 56 Digital Input Data Timing Specifications ............................... 10 NCO Only Mode ........................................................................ 60 JESD204B Interface Electrical and Speed Specifications ...... 11 Modulator Switch ....................................................................... 61 Input Data Rates and Signal Bandwidth Specifications ........ 12 Interrupt Request Operation ........................................................ 65 AC Specifications ........................................................................ 13 Interrupt Service Routine .......................................................... 65 Absolute Maximum Ratings .......................................................... 15 Analog Interface ............................................................................. 66 Reflow Profile .............................................................................. 15 DAC Input Clock Configurations ............................................ 66 Thermal Characteristics ............................................................ 15 Clock Output Driver .................................................................. 68 ESD Caution ................................................................................ 15 Analog Outputs .......................................................................... 68 Pin Configuration and Function Descriptions ........................... 16 Applications Information .............................................................. 70 Typical Performance Characteristics ........................................... 19 Hardware Considerations ......................................................... 70 Terminology .................................................................................... 27 Start-Up Sequence .......................................................................... 73 Theory of Operation ...................................................................... 28 Register Summary .......................................................................... 80 Serial Port Operation ..................................................................... 30 Register Details ............................................................................... 88 Data Format ................................................................................ 30 Outline Dimensions ..................................................................... 151 Serial Port Pin Descriptions ...................................................... 30 Ordering Guide ........................................................................ 151 Serial Port Options ..................................................................... 31 REVISION HISTORY 8/2019Rev. A to Rev. B Change to Figure 16 Caption ........................................................ 21 Changes to Digital Gain Section ................................................... 53 Changes to Figure 17 Caption ...................................................... 21 Changes to Figure 73 and Table 37 ............................................... 54 Changes to Table 17 ....................................................................... 33 Change to TB1 Parameter, Table 43 ............................................. 58 Changes to SYSREF Sampling Section ...................................... 41 Changes to NCO Only Mode Section .......................................... 60 Changes to Subclass 1 Section ...................................................... 42 Change to DAC Full-Scale Power Section ................................... 68 Change to Table 37 ......................................................................... 54 Changes to Table 55 ........................................................................ 76 Change to Complex Modulator Switch Configuration Changes to Table 56 ........................................................................ 77 S ection .............................................................................................. 63 Changes to Table 61 ........................................................................ 88 Changes to DAC On-Chip PLL Section ...................................... 67 Changes to Table 51 ....................................................................... 73 5/2019Rev. 0 to Rev. A Changes to Table 60 ....................................................................... 80 Changes to General Description Section ...................................... 1 Changes to Table 61 ....................................................................... 88 Change to Table 8 ........................................................................... 12 Changes to Table 9 .......................................................................... 14 11/2018Revision 0: Initial Version Rev. B Page 2 of 151