Data Sheet AD9177 Quad, 16-Bit, 12 GSPS RF DAC with Wideband Channelizers FEATURES Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Flexible, reconfigurable common platform design Phased array radar and electronic warfare 4 DAC cores connected to various DSP and bypass datapaths Electronic test and measurement systems Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable GENERAL DESCRIPTION On-chip PLL with multichip synchronization The AD9177 is a highly integrated device with four 16-bit, 12 External RFCLK input option for off-chip PLL GSPS maximum sample rate, RF digital-to-analog converter (DAC) Maximum DAC sample rate up to 12 GSPS cores supporting up to eight baseband channels. The device is well Maximum data rate up to 12 GSPS using JESD204C suited for applications requiring wideband DACs to process signals Useable analog bandwidth to 8 GHz of wide instantaneous bandwidth. The device features an 8-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data receiver DAC ac performance at 12 GSPS (JRx) port, an on-chip clock multiplier, and digital signal processing Full-scale output current range: 6.43 mA to 37.75 mA (DSP) datapaths capable of processing complex signals for wide- Two-tone IMD3 (7 dBFS per tone): 78.9 dBc band or multiband direct to RF applications, phase array radar NSD, single-tone at 3.7 GHz: 155.1 dBc/Hz systems, and electronic warfare applications. The DSP datapaths SFDR, single-tone at 3.7 GHz: 70 dBc can be bypassed to allow a direct connection between the data Versatile digital features receiver port and the DAC cores. Selectable interpolation filters For direct digital synthesis (DDS) applications, the AD9177 can Configurable or bypassable DUCs be operated without a data receiver port to generate multiple sine wave tones of varying frequencies. The main numerically 8 fine complex DUCs and 4 coarse complex DUCs controlled oscillator (NCO) block inside each of the four course 48-bit NCO per DUC digital upconverters (DUCs) contains one 48-bit NCO and a bank Option to bypass fine and coarse DUC of thirty one 32-bit NCOs, each with an independent phase accu- Programmable delay per datapath mulator. Similarly, the main NCO block inside each of the course and fine digital downconverters (DDCs) in the receive datapath Transmit DPD support contains a bank of sixteen 48-bit NCOs that can be looped into the Fine DUC channel gain control and delay adjust transmit datapath for processing ahead of the course DUCs and Auxiliary features DAC outputs. Combined with general-purpose input/output (GPIO) Direct digital synthesis and fast frequency hopping controls for frequency hopping, preconfigurable profile selection, and the ability to synchronize the NCOs to a common trigger using Low latency loopback mode (receive datapath NCO outputs the SYSREF input port, this bank allows phase coherent fast fre- can be routed to the transmit datapaths) quency hopping (FFH) for applications where multiple devices are Power amplifier downstream protection circuitry synchronized or where NCO frequencies are continuously adjusted On-chip temperature monitoring unit during operation. Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface 8-lane JESD204B/C receiver (JRx) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm 15 mm, 324-ball BGA with 0.8 mm pitch APPLICATIONS Wireless communications infrastructure Microwave point to point, E-band and 5G mmWave Rev. A Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet AD9177 TABLE OF CONTENTS Features................................................................ 1 CMOS Pin Specifications................................... 9 Applications........................................................... 1 DAC AC Specifications.......................................9 General Description...............................................1 Timing Specifications....................................... 12 Functional Block Diagram......................................3 Absolute Maximum Ratings.................................14 Specifications........................................................ 4 Thermal Resistance......................................... 14 Recommended Operating Conditions................ 4 ESD Caution.....................................................14 Power Consumption...........................................4 Pin Configuration and Function Descriptions...... 15 DAC DC Specifications...................................... 5 Typical Performance Characteristics...................18 Clock Inputs and Outputs...................................6 DAC..................................................................18 Clock Input and Phase-Locked Loop (PLL) Theory of Operation.............................................23 Frequency Specifications................................. 6 Applications Information...................................... 24 DAC Sample Rate Specifications.......................7 Outline Dimensions............................................. 25 Input Data Rate Specifications...........................7 Ordering Guide.................................................25 NCO Frequency Specifications.......................... 8 Evaluation Boards............................................ 25 JESD204B and JESD204C Interface Electrical and Speed Specifications................. 8 REVISION HISTORY 7/2021Rev. 0 to Rev. A Changes to Data Sheet Title and Features Section.........................................................................................1 6/2021Revision 0: Initial Version analog.com Rev. A 2 of 25