14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9208 FEATURES 2 integrated, wideband digital processors per channel 48-bit NCO JESD204B (Subclass 1) coded serial digital outputs 4 cascaded half-band filters Support for lane rates up to 16 Gbps per lane Phase coherent NCO switching 1.65 W total power per channel at 3 GSPS (default settings) Up to 4 channels available Performance at 2 dBFS amplitude, 2.6 GHz input Serial port control SFDR = 70 dBFS Integer clock with divide by 2 and divide by 4 options SNR = 57.2 dBFS Flexible JESD204B lane configurations Performance at 9 dBFS amplitude, 2.6 GHz input On-chip dither SFDR = 78 dBFS SNR = 59.5 dBFS APPLICATIONS Integrated input buffer Diversity multiband and multimode digital receivers Noise density = 152 dBFS/Hz 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A 0.975 V, 1.9 V, and 2.5 V dc supply operation Electronic test and measurement systems 9 GHz analog input full power bandwidth (3 dB) Phased array radar and electronic warfare Amplitude detect bits for efficient AGC implementation DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD1 DRVDD2 SPIVDD (0.975V) (1.9V) (2.5V) (0.975V) (0.975V) (0.975V) (1.9V) (1.9V) BUFFER 14 VIN+A ADC CORE VINA SERDOUT0 DIGITAL DOWN- CONVERTER SERDOUT1 JESD204B SERDOUT2 8 FAST SIGNAL LINK SERDOUT3 DETECT MONITOR AND SERDOUT4 Tx DIGITAL DOWN- SERDOUT5 OUTPUTS CONVERTER SERDOUT6 14 VIN+B SERDOUT7 ADC VINB CORE BUFFER VREF SYNCINB PDWN/STBY JESD204B CLOCK FD A/GPIO A0 SYSREF SUBCLASS 1 DISTRIBUTION CONTROL GPIO A1 GPIO MUX CLK+ FD B/GPIO B0 SPI AND GPIO B1 CONTROL REGISTERS CLK 2 4 AD9208 AGND SDIO SCLK CSB DRGND DGND Figure 1. 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PROGRAMMABLE FIR FILTER CROSSBAR MUX CROSSBAR MUX 15547-001AD9208 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Complex to Real Conversion ......................................... 57 Applications ....................................................................................... 1 DDC Mixed Decimation Settings ............................................ 58 Functional Block Diagram .............................................................. 1 DDC Example Configurations ................................................. 59 Revision History ............................................................................... 3 DDC Power Consumption ........................................................ 63 General Description ......................................................................... 4 Signal Monitor ................................................................................ 64 Specif icat ions ..................................................................................... 5 SPORT over JESD204B .............................................................. 65 DC Specifications ......................................................................... 5 Digital Outputs ............................................................................... 67 AC Specifications .......................................................................... 6 Introduction to the JESD204B Interface ................................. 67 Digital Specifications ................................................................... 7 JESD204B Overview .................................................................. 67 Switching Specifications .............................................................. 9 Functional Overview ................................................................. 68 Timing Specifications ................................................................ 10 JESD204B Link Establishment ................................................. 68 Absolute Maximum Ratings .......................................................... 12 Physical Layer (Driver) Outputs .............................................. 70 Thermal Resistance .................................................................... 12 f 4 Mode .................................................................................. 71 S ESD Caution ................................................................................ 12 Setting Up the AD9208 digital interface .................................. 72 Pin Configuration and Function Descriptions ........................... 13 Deterministic Latency .................................................................... 78 Typical Performance Characteristics ........................................... 16 Subclass 0 Operation .................................................................. 78 Equivalent Circuits ......................................................................... 22 Subclass 1 Operation .................................................................. 78 Theory of Operation ...................................................................... 24 Multichip Synchronization ............................................................ 80 ADC Architecture ...................................................................... 24 Normal Mode .............................................................................. 80 Analog Input Considerations .................................................... 24 Timestamp Mode ....................................................................... 80 Voltage Reference ....................................................................... 28 SYSREF Input .............................................................................. 82 DC Offset Calibration ................................................................ 29 SYSREF Setup/Hold Window Monitor ................................. 84 Clock Input Considerations ...................................................... 29 Latency ............................................................................................. 86 Power-Down/Standby Mode..................................................... 31 End to End Total Latency .......................................................... 86 Temperature Diode .................................................................... 31 Example Latency Calculations.................................................. 86 ADC Overrange and Fast Detect .................................................. 33 LMFC Referenced Latency ........................................................ 86 ADC Overrange .......................................................................... 33 Test Modes ....................................................................................... 88 Fast Threshold Detection (FD A and FD B) ........................ 33 ADC Test Modes ........................................................................ 88 ADC Application Modes and JESD204B Tx Converter Mapping JESD204B Block Test Modes .................................................... 89 ........................................................................................................... 34 Serial Port Interface ........................................................................ 91 Programmable FIR filters .............................................................. 36 Configuration Using the SPI ..................................................... 91 Supported Modes........................................................................ 36 Hardware Interface ..................................................................... 91 Programming Instructions ........................................................ 38 SPI Accessible Features .............................................................. 91 Digital Downconverter (DDC) ..................................................... 40 Memory Map .................................................................................. 92 DDC I/Q Input Selection .......................................................... 40 Reading the Memory Map Register Table ............................... 92 DDC I/Q Output Selection ....................................................... 40 Memory Map Register Details .................................................. 93 DDC General Description ........................................................ 40 Applications Information ............................................................ 134 DDC Frequency Translation ..................................................... 43 Power Supply Recommendations ........................................... 134 DDC Decimation Filters ............................................................ 51 Layout Guidelines..................................................................... 135 DDC Gain Stage ......................................................................... 57 AVDD1 SR (Pin E7) and AGND (Pin E6 and Pin E8) ........... 135 Rev. 0 Page 2 of 136