Quad, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS 1.8 V ADC Data Sheet AD9219 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN 4 ADCs integrated into 1 package DRVDD DRGND 94 mW ADC power per channel at 65 MSPS AD9219 10 SNR = 60 dB (to Nyquist) VIN + A SERIAL D + A PIPELINE ENOB = 9.7 bits D A LVDS VIN A ADC SFDR = 78 dBc (to Nyquist) 10 VIN + B PIPELINE SERIAL D + B Excellent linearity D B VIN B ADC LVDS DNL = 0.2 LSB (typical) 10 VIN + C SERIAL INL = 0.3 LSB (typical) PIPELINE D + C D C VIN C LVDS ADC Serial LVDS (ANSI-644, default) 10 Low power, reduced signal option (similar to IEEE 1596.3) VIN + D SERIAL PIPELINE D + D LVDS D D VIN D ADC Data and frame clock outputs VREF 315 MHz full-power analog bandwidth SENSE FCO+ 2 V p-p input voltage range + 0.5V FCO DATA RATE 1.8 V supply operation REFT REF MULTIPLIER SERIAL PORT DCO+ REFB SELECT Serial port control INTERFACE DCO Full-chip and individual-channel power-down modes Flexible bit orientation RBIASAGND CSB SDIO/ODM SCLK/DTP CLK+ CLK Built-in and custom digital test pattern generation Figure 1. Programmable clock and data alignment The ADC automatically multiplies the sample rate clock for the Programmable output resolution appropriate LVDS serial data rate. A data clock output (DCO) for Standby mode capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel APPLICATIONS power-down is supported and typically consumes less than Medical imaging and nondestructive ultrasound 2 mW when all channels are disabled. Portable ultrasound and digital beam-forming systems Quadrature radio receivers The ADC contains several features designed to maximize flexibility Diversity radio receivers and minimize system cost, such as programmable clock and data Tape drives alignment and programmable digital test pattern generation. The Optical networking available digital test patterns include built-in deterministic and Test equipment pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). GENERAL DESCRIPTION The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con- The AD9219 is available in a RoHS compliant, 48-lead LFCSP. It is verter (ADC) with an on-chip sample-and-hold circuit designed specified over the industrial temperature range of 40C to +85C. for low cost, low power, small size, and ease of use. The product PRODUCT HIGHLIGHTS operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications 1. Small Footprint. Four ADCs are contained in a small, space- where a small package size is critical. saving package. 2. Low power of 94 mW/channel at 65 MSPS. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. Ease of Use. A data clock output (DCO) is provided that CMOS-/LVDS-compatible sample rate clock for full performance operates at frequencies of up to 390 MHz and supports operation. No external reference or driver components are double data rate (DDR) operation. required for many applications. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20062020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 05726-001AD9219 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 20 Applications ...................................................................................... 1 Clock Input Considerations ..................................................... 23 General Description ......................................................................... 1 Serial Port Interface (SPI) ............................................................. 31 Functional Block Diagram .............................................................. 1 Hardware Interface .................................................................... 31 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 33 Revision History ............................................................................... 2 Reading the Memory Map Table ............................................. 33 Specifications .................................................................................... 4 Reserved Locations .................................................................... 33 AC Specifications ......................................................................... 5 Default Values ............................................................................ 33 Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 33 Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 37 Timing Diagrams .............................................................................. 8 Power Supplies ........................................................................... 37 Absolute Maximum Ratings ......................................................... 10 Input Signals ............................................................................... 37 Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 37 ESD Caution................................................................................ 10 Default Operation and Jumper Selection Settings ................ 38 Pin Configuration and Function Descriptions .......................... 11 Alternative Analog Input Drive Configuration ..................... 39 Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 53 Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 53 Theory of Operation ...................................................................... 20 REVISION HISTORY 5/2010Rev. C to Rev. D 9/2020Rev. F to Rev. G Updated Outline Dimensions ...................................................... 52 Changed CP-48-8 to CP-48-9 ...................................... Throughout Changes to Ordering Guide .......................................................... 52 Changes to Figure 5 ........................................................................ 11 Updated Outline Dimensions ....................................................... 53 4/2010Rev. B to Rev. C Changes to Ordering Guide .......................................................... 53 Changes to Table 16 ....................................................................... 33 Updated Outline Dimensions ...................................................... 52 9/2018Rev. E to Rev. F Changes to Figure 5 and Table 7 .................................................. 11 7/2007Rev. A to Rev. B Changes to Digital Outputs and Timing Section ....................... 28 Changes to Figure 2 and Figure 4 ................................................... 7 Updated Outline Dimensions ....................................................... 53 Changes to Table 17 ....................................................................... 50 Changes to Ordering Guide .......................................................... 53 5/2007Rev. 0 to Rev. A Changes to Features .......................................................................... 1 12/2011Rev. D to Rev. E Changes to Logic Output (SDIO/ODM) Section ......................... 5 Added Exposed Pad Notation to Figure 5 .................................. 11 Added Endnote 3 to Table 3 ............................................................ 5 Changes to Output Signals Section and Figure 71..................... 37 Changes to Pipeline Latency ............................................................ 6 Change to Default Operation and Jumper Selection Settings Changes to Figure 2 to Figure 4 ...................................................... 7 Section .............................................................................................. 38 Changes to Figure 10 ..................................................................... 12 Change to Figure 74 ....................................................................... 41 Changes to Figure 15, Figure 23 to Figure 26 Captions ............ 14 Changed LFCSP WQ to LFCSP VQ Throughout ................... 53 Changes to Figure 16, Figure 37, Figure 39, and Figure 40 ...... 14 Added Endnote 2 in Ordering Guide .......................................... 53 Added Figure 46 and Figure 47 .................................................... 20 Rev. G Page 2 of 53