Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter Data Sheet AD9222 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS AD9222 12 SNR = 70 dB (to Nyquist) VIN + A D + A SERIAL ADC D A LVDS VIN A ENOB = 11.3 bits 12 SFDR = 80 dBc VIN + B D + B SERIAL ADC D B VIN B LVDS Excellent linearity: DNL = 0.3 LSB (typical), 12 INL = 0.4 LSB (typical) VIN + C D + C SERIAL ADC LVDS D C VIN C Serial LVDS (ANSI-644, default) 12 Low power, reduced signal option (similar IEEE 1596.3) VIN + D SERIAL D + D ADC LVDS D D VIN D Data and frame clock outputs 12 325 MHz full-power analog bandwidth VIN + E SERIAL D + E ADC D E VIN E LVDS 2 V p-p input voltage range 12 1.8 V supply operation VIN + F D + F SERIAL ADC VIN F LVDS D F Serial port control 12 Full-chip and individual-channel power-down modes VIN + G D + G SERIAL ADC LVDS D G Flexible bit orientation VIN G Built-in and custom digital test pattern generation 12 VIN + H D + H SERIAL ADC Programmable clock and data alignment LVDS VIN H D H Programmable output resolution VREF Standby mode SENSE FCO + 0.5V FCO DATA RATE REFT REF MULTIPLIER APPLICATIONS SERIAL PORT DCO + REFB SELECT INTERFACE DCO Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK ODM DTP Quadrature radio receivers Figure 1. Diversity radio receivers Tape drives The ADC contains several features designed to maximize Optical networking flexibility and minimize system cost, such as programmable Test equipment clock and data alignment and programmable digital test pattern GENERAL DESCRIPTION generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to- defined test patterns entered via the serial port interface (SPI). digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is use. The product operates at a conversion rate of up to 65 MSPS specified over the industrial temperature range of 40C to +85C. and is optimized for outstanding dynamic performance and low PRODUCT HIGHLIGHTS power in applications where a small package size is critical. 1. Small Footprint. Eight ADCs are contained in a small, The ADC requires a single 1.8 V power supply and LVPECL-/ space-saving package. CMOS-/LVDS-compatible sample rate clock for full performance 2. Low power of 114 mW/channel at 65 MSPS. operation. No external reference or driver components are 3. Ease of Use. A data clock output (DCO) is provided that required for many applications. operates at frequencies of up to 390 MHz and supports The ADC automatically multiplies the sample rate clock for double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock output (DCO) 4. User Flexibility. The SPI control offers a wide range of for capturing data on the output and a frame clock output (FCO) flexible features to meet specific system requirements. for signaling a new output byte are provided. Individual-channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit) power-down is supported and typically consumes less than and AD9252 (14-bit). 2 mW when all channels are disabled. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20062011 Analog Devices, Inc. All rights reserved. 05967-001AD9222 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 33 Functional Block Diagram .............................................................. 1 Hardware Interface ..................................................................... 34 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 36 Revision History ............................................................................... 2 Reading the Memory Map Table .............................................. 36 Specifications ..................................................................................... 3 Reserved Locations .................................................................... 36 AC Specifications .......................................................................... 4 Default Values ............................................................................. 36 Digital Specifications ................................................................... 5 Logic Levels ................................................................................. 36 Switching Specifications .............................................................. 6 Evaluation Board ............................................................................ 40 Timing Diagrams .............................................................................. 7 Power Supplies ............................................................................ 40 Absolute Maximum Ratings ............................................................ 9 Input Signals................................................................................ 40 Thermal Impedance ..................................................................... 9 Output Signals ............................................................................ 40 ESD Caution .................................................................................. 9 Default Operation and Jumper Selection Settings ................. 41 Pin Configuration and Function Descriptions ........................... 10 Alternative Analog Input Drive Configuration...................... 42 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 59 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 59 Theory of Operation ...................................................................... 21 REVISION HISTORY 12/11Rev E to Rev. F Changes to Figure 2 to Figure 4 ....................................................... 7 Changes to Figure 86 ...................................................................... 41 Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30, Changes to Ordering Guide .......................................................... 59 Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44, Figure 46, Figure 48, and Figure 51 .............................................. 15 11/11Rev. D to Rev. E Added Figure 56 and Figure 58 .................................................... 22 Changes to Output Signals Section .............................................. 41 Added Figure 70 ............................................................................. 25 Changes to Figure 86 ...................................................................... 41 Added Figure 72 ............................................................................. 26 Changes to Ordering Guide .......................................................... 60 Added Figure 74 ............................................................................. 27 4/10Rev. C to Rev. D Added Figure 76 and Figure 78 .................................................... 28 Changes to Digital Outputs and Timing Section ....................... 28 Changes to Address 16 in Table 16 ............................................... 38 Changes to Table 9 Endnote .......................................................... 29 Updated Outline Dimensions ....................................................... 59 Added Table 10 ............................................................................... 30 Changes to Ordering Guide .......................................................... 59 Changes to RBIAS Pin Section ..................................................... 31 1/10Rev. B to Rev. C Deleted Figure 56 and Figure 57................................................... 27 Updated Outline Dimensions ....................................................... 59 Changes to Table 15 ....................................................................... 35 Changes to Ordering Guide .......................................................... 60 Change to Input Signals Section ................................................... 40 Change to Output Signals Section................................................ 40 7/09Rev. A to Rev. B Changes to Figure 86 ...................................................................... 40 Changes to Figure 5 ........................................................................ 10 Changes to Default Operation and Jumper Selection Changes to Figure 61 and Figure 62 ............................................. 23 Settings Section ............................................................................... 41 Changes to Figure 79 and Figure 80 ............................................. 31 Changes to Alternative Analog Input Configuration Section ......... 42 Updated Outline Dimensions ....................................................... 59 Added Figure 88 and Figure 89 .................................................... 42 Changes to Ordering Guide .......................................................... 59 Change to Figure 92 ....................................................................... 45 8/07Rev. 0 to Rev. A Changes to Table 17 ....................................................................... 54 Added 65 MSPS Models .................................................... Universal Updated Outline Dimensions ....................................................... 59 Changes to Features .......................................................................... 1 Changes to Ordering Guide .......................................................... 60 Changes to Product Highlights ....................................................... 1 9/06Revision 0: Initial Version Rev. F Page 2 of 60